AN 1011: TinyML Applications in Altera FPGAs Using LiteRT for Microcontrollers

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ID 848984
Date 4/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Preparing LiteRT Inference Model 3. Generating Nios® V Processor System 4. Generating Arm Processor System 5. Programming and Running 6. Appendix 7. Document Revision History for the AN 1011: TinyML Applications in Altera FPGAs Using LiteRT for Microcontrollers
1. Overview x
1.1. Requirements
2. Preparing LiteRT Inference Model x
2.1. Defining the Problem 2.2. Gathering and Preparing Sample Data 2.3. Building TensorFlow Model 2.4. Preparing the LiteRT Model 2.5. Preparing Binaries for C/C++
2.2. Gathering and Preparing Sample Data x
2.2.1. Preparing Dataset 2.2.2. Preprocessing Dataset
2.3. Building TensorFlow Model x
2.3.1. Constructing Model Architecture 2.3.2. Configuring Model 2.3.3. Training Model 2.3.4. Evaluating the Model 2.3.5. Saving and Loading Model
2.4. Preparing the LiteRT Model x
2.4.1. Converting into LiteRT Model 2.4.2. Saving the LiteRT Model 2.4.3. Analyzing the LiteRT Model 2.4.4. Loading a LiteRT Interpreter 2.4.5. Evaluating the LiteRT Model
2.5. Preparing Binaries for C/C++ x
2.5.1. Converting LiteRT to a C Array 2.5.2. Preparing a Header File for LiteRT C Array 2.5.3. Preparing Supporting Header File for LiteRT C Array 2.5.4. Preparing Main Function to Run TinyML 2.5.5. Converting MNIST Sample into C Array
3. Generating Nios® V Processor System x
3.1. Building Hardware Design in Platform Designer 3.2. Building Software Design with Ashling* RiscFree* IDE for Altera® FPGAs
3.2. Building Software Design with Ashling* RiscFree* IDE for Altera® FPGAs x
3.2.1. Creating a Board Support Package 3.2.2. Building LiteRT for Microcontroller Static Library 3.2.3. Creating an Application Project File 3.2.4. Building the LiteRT TinyML Application
4. Generating Arm Processor System x
4.1. GHRD Hardware Design 4.2. Building the Software Design
4.2. Building the Software Design x
4.2.1. Arm-Trusted-Firmware 4.2.2. Building LiteRT for Microcontrollers Static Library 4.2.3. Zephyr OS Environment Setup 4.2.4. Building the LiteRT TinyML Application
4.2.1. Arm-Trusted-Firmware x
4.2.1.1. Booting from QSPI Flash 4.2.1.2. Running through Ashling* RiscFree* IDE for Altera® FPGAs Debugger
5. Programming and Running x
5.1. Nios® V Processor System 5.2. Arm HPS Processor System
5.2. Arm HPS Processor System x
5.2.1. Booting from QSPI 5.2.2. Booting via the Debugger
6. Appendix x
6.1. main.cc for Nios V Processor 6.2. main.cc for Arm HPS Processor
1. Overview
2. Preparing LiteRT Inference Model
3. Generating Nios® V Processor System
4. Generating Arm Processor System
5. Programming and Running
6. Appendix
7. Document Revision History for the AN 1011: TinyML Applications in Altera FPGAs Using LiteRT for Microcontrollers

5.2. Arm HPS Processor System

You can run the application on HPS either through QSPI flash boot or using the Ashling* RiscFree* IDE for Altera® FPGAs debugger tool. Before starting any process, ensure you have the necessary binary files ready to program the QSPI or run via the debugger. Refer to the following steps:
  1. Create a new directory. Name it tinyml_bins.
    $ cd $TOP_FOLDER
$ mkdir tinyml_bins
  2. Generate the fiptool from ATF repository downloaded in section Arm-Trusted-Firmware. Use this tool to create the binary file that combines the SSBL (bl31.bin) and Zephyr application (zephyr.bin).
    $ cd $TOP_FOLDER/atf_tinyml
$ ARCH=arm64 CROSS_COMPILE=aarch64-none-linux-gnu- make fiptool
$ cp tools/fiptool/fiptool $TOP_FOLDER/tinyml_bins
  3. Copy the bootloader files to the tinyml_bins.
    $ cd $TOP_FOLDER/atf_tinyml/build/agilex5/<release_or_debug>
$ cp bl2.bin bl31 $TOP_FOLDER/tinyml_bins
  4. Copy the generated .sof file from the GHRD according to the steps in the topic GHRD Hardware Design.
    $ cd $TOP_FOLDER/agilex5_soc_devkit/ 
$ cp ghrd_a5ed065bb32ae6sr0.sof $TOP_FOLDER/tinyml_bins

Section Content
Booting from QSPI
Booting via the Debugger

Level Two Title