AN 1011: TinyML Applications in Altera FPGAs Using LiteRT for Microcontrollers

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ID 848984
Date 4/07/2025
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Document Table of Contents
Document Table of Contents x
1. Overview 2. Preparing LiteRT Inference Model 3. Generating Nios® V Processor System 4. Generating Arm Processor System 5. Programming and Running 6. Appendix 7. Document Revision History for the AN 1011: TinyML Applications in Altera FPGAs Using LiteRT for Microcontrollers
1. Overview x
1.1. Requirements
2. Preparing LiteRT Inference Model x
2.1. Defining the Problem 2.2. Gathering and Preparing Sample Data 2.3. Building TensorFlow Model 2.4. Preparing the LiteRT Model 2.5. Preparing Binaries for C/C++
2.2. Gathering and Preparing Sample Data x
2.2.1. Preparing Dataset 2.2.2. Preprocessing Dataset
2.3. Building TensorFlow Model x
2.3.1. Constructing Model Architecture 2.3.2. Configuring Model 2.3.3. Training Model 2.3.4. Evaluating the Model 2.3.5. Saving and Loading Model
2.4. Preparing the LiteRT Model x
2.4.1. Converting into LiteRT Model 2.4.2. Saving the LiteRT Model 2.4.3. Analyzing the LiteRT Model 2.4.4. Loading a LiteRT Interpreter 2.4.5. Evaluating the LiteRT Model
2.5. Preparing Binaries for C/C++ x
2.5.1. Converting LiteRT to a C Array 2.5.2. Preparing a Header File for LiteRT C Array 2.5.3. Preparing Supporting Header File for LiteRT C Array 2.5.4. Preparing Main Function to Run TinyML 2.5.5. Converting MNIST Sample into C Array
3. Generating Nios® V Processor System x
3.1. Building Hardware Design in Platform Designer 3.2. Building Software Design with Ashling* RiscFree* IDE for Altera® FPGAs
3.2. Building Software Design with Ashling* RiscFree* IDE for Altera® FPGAs x
3.2.1. Creating a Board Support Package 3.2.2. Building LiteRT for Microcontroller Static Library 3.2.3. Creating an Application Project File 3.2.4. Building the LiteRT TinyML Application
4. Generating Arm Processor System x
4.1. GHRD Hardware Design 4.2. Building the Software Design
4.2. Building the Software Design x
4.2.1. Arm-Trusted-Firmware 4.2.2. Building LiteRT for Microcontrollers Static Library 4.2.3. Zephyr OS Environment Setup 4.2.4. Building the LiteRT TinyML Application
4.2.1. Arm-Trusted-Firmware x
4.2.1.1. Booting from QSPI Flash 4.2.1.2. Running through Ashling* RiscFree* IDE for Altera® FPGAs Debugger
5. Programming and Running x
5.1. Nios® V Processor System 5.2. Arm HPS Processor System
5.2. Arm HPS Processor System x
5.2.1. Booting from QSPI 5.2.2. Booting via the Debugger
6. Appendix x
6.1. main.cc for Nios V Processor 6.2. main.cc for Arm HPS Processor
1. Overview
2. Preparing LiteRT Inference Model
3. Generating Nios® V Processor System
4. Generating Arm Processor System
5. Programming and Running
6. Appendix
7. Document Revision History for the AN 1011: TinyML Applications in Altera FPGAs Using LiteRT for Microcontrollers

5.2.2. Booting via the Debugger

Use the Quartus® Prime Programmer tool and the Ashling* RiscFree* IDE for Altera® FPGAs to program the Arm HPS processor-based system (hardware and software system respectively) into the FPGA and to run your application.
  1. Make sure you set MSEL dipswitch SW27 to JTAG: (OFF-OFF-OFF-OFF). Then connect the HPS UART to a terminal on your machine, like Putty or MobaXterm on Windows, or Minicom on Linux.
  2. Add the BL2 FSBL to the generated GHRD .sof file. First, convert bl2.bin file into a hex format, then use quartus_pfg to embed the hex format of BL2 with ghrd .sof file, and create the .rbf format file per the following steps: 
    $ cd $TOP_FOLDER/tinyml_bins
$ aarch64-none-linux-gnu-objcopy -v -I binary -O ihex --change-addresses 0x0 
bl2.bin  bl2.hex
$ quartus_pfg -c ghrd_a5ed065bb32ae6sr0.sof ghrd.rbf -o hps=1 -o 
hps_path=bl2.hex

    The quartus_pfg command converts the .sof file into two .rbf files: the core and the hps files. Use the core file to configure the FPGA fabric, while the hps file to configure the HPS IO.

  3. Use the -o hps_path argument to guide the tool to the location of the FSBL and embed it with the ghrd.hps.rbf file. Ashling* RiscFree* IDE for Altera® FPGAs debugger tool loads the bl31.bin file to the board. To run the application on board, program the device with the following generated .rbf bitstream: 
    quartus_pgm -c 1 -m jtag -o "p;ghrd.hps.rbf"
    Once the process is complete, you can see the FSBL boot on the HPS terminal. The last message indicates that FSBL was booted successfully, and it is waiting for SSBL to load using the debugger tool.
    Figure 24. BL2 Boot on HPS Terminal (Debugger Flow)
  4. Next, open Ashling* RiscFree* IDE for Altera® FPGAs tool, set your workspace directory, and copy the required binary files generated earlier: bl31.bin, zephyr.bin, and zephyr.elf (if debug is needed). From Run menu, go to Debug Configuration.
    Figure 25.  Ashling* RiscFree* IDE for Altera® FPGAs Menus
  5. Select Ashling Heterogeneous Multicore Hardware Debugging, then configure the ARM Coresight SOC core 0.
    Figure 26. Heterogeneous Multicore Hardware Debugging Configuration 1
  6. Go to Target Application tab:
    • Add the .elf file if you need the debug information. Otherwise, you can run the application only.
    • Keep Load image unchecked (because you need to load it later manually).
    • Check Load symbols (if the .elf file is loaded for debugging).
  7. In Startup tab, keep everything to default. In OS Awareness tab, turn on Enable OS Aware Debugging and select Zephyr OS if you want to debug your application. You can ignore this step if you want to run the application only without debugging. Once done, click Apply > Debug. Your system should be ready to receive the binary files via Debugger Console.
    Figure 27. Heterogeneous Multicore Hardware Debugging Configuration 3
    Figure 28. Ashling RiscFree Debugger Console
    The commands required in Debugger Console: 
    The needed commands in Debugger Console can be seen below:

set debug remote 1
restore <Absoulte_Path_to_your_Workspace>/bl31_801.bin  binary 0x80000000
restore <Absoulte_Path_to_your_Workspace>/zephyr.bin  binary 0x80100000
set $x1=0

The set debug remote 1 command is used to enable message transaction acknowledgement 
from the board to indicate the download completion of a binary file. 
A sample screenshot can be seen below.
    Use the set debug remote 1 command to enable message transaction acknowledgement from the board to indicate the download completion of a binary file. Refer to the following example.
    Figure 29. Ashling RiscFree Debugger Console Output
  8. Use the restore command to load the binary file to its destination memory. In this example, the SSBL and Zephyr applications are loaded into HPS DDR memory. Make sure to use the same addresses in the commands above. Refer to the following sample screenshots of the application execution from the HPS UART terminal.
    Figure 30. Example Print Logs Part 1 - Setting up Zephyr and TinyML
    Figure 31. Example Print Logs Part 1 - Setting up Zephyr and TinyML
    Figure 32. Example Print Logs Part 3 - Classifying Image
    Figure 33. Example Print Logs Part 4 - Profiling TinyML model
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