Cyclone® V SoC Development Kit User Guide

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ID 830285
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Update Portal 5. Board Test System 6. Document Revision History for the Cyclone® V SoC Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents
2. Getting Started x
2.1. Before You Begin 2.2. Inspecting the Boards 2.3. Software and Driver Installation
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Standard Edition Software 2.3.2. Installing the Intel® SoC EDS 2.3.3. Installing the Development Kit 2.3.4. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Setting Up the Development Kit 3.2. Factory Default Switch and Jumper Settings 3.3. Restoring the MAX® V CPLD to the Factory Setting 3.4. Restoring CFI Flash Device to the Factory Defaults
3.2. Factory Default Switch and Jumper Settings x
3.2.1. Restoring the Default Settings for Power Solution 2 Board 3.2.2. Restoring the Default Settings for Power Solution 1 Board
4. Board Update Portal x
4.1. Connecting to the Board Update Portal Web Page
5. Board Test System x
5.1. Preparing the Board for the Board Test System 5.2. Running the Board Test System 5.3. Using the Board Test System 5.4. The Power Monitor 5.5. The Clock Control 5.6. Configuring the FPGA Using the Quartus® Prime Programmer
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The System Info Tab 5.3.3. The GPIO Tab 5.3.4. The I2C Tab 5.3.5. The DDR3 Tab 5.3.6. The SDI Video Tab 5.3.7. The HSMC Tab
5.6. Configuring the FPGA Using the Quartus® Prime Programmer x
5.6.1. Before Configuring 5.6.2. Configuring the FPGA
A. Development Kit Components x
A.1. Board Overview A.2. Programming Flash Memory A.3. Power
A.2. Programming Flash Memory x
A.2.1. CFI Flash Memory A.2.2. quad SPI Flash Memory A.2.3. SD Card Memory
A.2.1. CFI Flash Memory x
A.2.1.1. CFI Flash Memory Map A.2.1.2. Programming CFI Flash Using the Quartus® Prime Programmer A.2.1.3. Converting .sof Files to a .pof
A.2.2. quad SPI Flash Memory x
A.2.2.1. Programming quad SPI Flash Using the Quartus® Prime Programmer
A.2.3. SD Card Memory x
A.2.3.1. Programming the SD Card Boot Image
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Update Portal
5. Board Test System
6. Document Revision History for the Cyclone® V SoC Development Kit User Guide
A. Development Kit Components
B. Additional Information

5.5. The Clock Control

The Clock Control application sets the Si570 or Si571 programmable oscillators to any frequency between 10 MHz and 810 MHz and Si5338. The frequencies support eight digits of precision to the right of the decimal point.

The Clock Control application runs as a stand-alone application. ClockControl.bat resides in the cycloneVSX_5csxfc6df31_soc\examples\board_test_system directory.

For more information about the Si570/Si571/Si5338 and the Cyclone® V development board's clocking circuitry and clock input pins, refer to the Cyclone® V SoC Development Board Reference Manual .

The Clock Control communicates with the MAX® V device on the board through the JTAG bus. The Si570, Si571, and Si5338 programmable oscillators are connected to the MAX® V device through a 2-wire serial bus.

The following figure shows the Clock Control Si570 tab.

Figure 16. The Clock Control—Si570

The following sections describe the Clock Control controls.

Serial Port Registers

The Serial port registers control shows the current values from the Si570 registers.

For more information about the Si570 registers, refer to the Si570/Si571 data sheet available on the Skyworks website.

fXTAL

The fXTAL control shows the calculated internal fixed-frequency crystal, based on the serial port register values. For more information about the fXTAL value and how it is calculated, refer to the Si570/Si571 data sheet available on the Skyworks website.

Target Frequency

The Target frequency control allows you to specify the frequency of the clock. Legal values are between 10 and 810 MHz with eight digits of precision to the right of the decimal point. For example, 421.31259873 is possible within 100 parts per million (ppm). The Target frequency control works in conjunction with the Set New Frequency control.

Default

This control sets the frequency for the oscillator associated with the active tab back to its default value. This can also be accomplished by power cycling the board.

Set New Frequency

The Set New Frequency control sets the programmable oscillator frequency for the selected clock to the value in the Target frequency control for the Si570 and Si571. Frequency changes might take several milliseconds to take effect. You might see glitches on the clock during this time. Altera recommends that you reset the FPGA logic after changing the frequencies.

Figure 17. The Clock Control—Si5338
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