Cyclone® V SoC Development Kit User Guide

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ID 830285
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Update Portal 5. Board Test System 6. Document Revision History for the Cyclone® V SoC Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents
2. Getting Started x
2.1. Before You Begin 2.2. Inspecting the Boards 2.3. Software and Driver Installation
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Standard Edition Software 2.3.2. Installing the Intel® SoC EDS 2.3.3. Installing the Development Kit 2.3.4. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Setting Up the Development Kit 3.2. Factory Default Switch and Jumper Settings 3.3. Restoring the MAX® V CPLD to the Factory Setting 3.4. Restoring CFI Flash Device to the Factory Defaults
3.2. Factory Default Switch and Jumper Settings x
3.2.1. Restoring the Default Settings for Power Solution 2 Board 3.2.2. Restoring the Default Settings for Power Solution 1 Board
4. Board Update Portal x
4.1. Connecting to the Board Update Portal Web Page
5. Board Test System x
5.1. Preparing the Board for the Board Test System 5.2. Running the Board Test System 5.3. Using the Board Test System 5.4. The Power Monitor 5.5. The Clock Control 5.6. Configuring the FPGA Using the Quartus® Prime Programmer
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The System Info Tab 5.3.3. The GPIO Tab 5.3.4. The I2C Tab 5.3.5. The DDR3 Tab 5.3.6. The SDI Video Tab 5.3.7. The HSMC Tab
5.6. Configuring the FPGA Using the Quartus® Prime Programmer x
5.6.1. Before Configuring 5.6.2. Configuring the FPGA
A. Development Kit Components x
A.1. Board Overview A.2. Programming Flash Memory A.3. Power
A.2. Programming Flash Memory x
A.2.1. CFI Flash Memory A.2.2. quad SPI Flash Memory A.2.3. SD Card Memory
A.2.1. CFI Flash Memory x
A.2.1.1. CFI Flash Memory Map A.2.1.2. Programming CFI Flash Using the Quartus® Prime Programmer A.2.1.3. Converting .sof Files to a .pof
A.2.2. quad SPI Flash Memory x
A.2.2.1. Programming quad SPI Flash Using the Quartus® Prime Programmer
A.2.3. SD Card Memory x
A.2.3.1. Programming the SD Card Boot Image
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Update Portal
5. Board Test System
6. Document Revision History for the Cyclone® V SoC Development Kit User Guide
A. Development Kit Components
B. Additional Information

3.2.1. Restoring the Default Settings for Power Solution 2 Board

Figure 5. Switch Locations and Default Settings for Power Solution 2 Board

To restore Cyclone® V SoC Development Kit (Power Solution 2) board switches to their factory default settings, perform these steps:

  1. Set the DIP switch bank (SW2) to match the SW2 DIP Switch Settings table.

    In the following table, ON indicates the switch is to the left according to the board orientation as shown in the Switch Locations and Default Settings for Power Solution 2 figure.

    Table 3.  SW2 DIP Switch Settings
    Switch Board Label Function Default Position
    1 CLK125A Switch 1 has the following options:
    • ON (0)—Onboard oscillator is disabled.
    • OFF (1)—Onboard oscillator is enabled.
    		 OFF
    2 Si570 Switch 2 has the following options:
    • ON (0)—Onboard programmable oscillator is enabled.
    • OFF (1)—Onboard programmable oscillator is disabled.
    		 ON
    3 FACT LOAD Switch 4 has the following options:
    • ON (0)—Load the factory design starting at 0x20000 at power up.
    • OFF (1)—Parallel flash loader (PFL) disabled.
    		 OFF
    4 Security Switch 4 has the following options:
    • ON (0)—Onboard Intel® FPGA Download Cable II sends FACTORY command at power up.
    • OFF (1)—Onboard Intel® FPGA Download Cable II does not send FACTORY command at power up.
    		OFF
  2. Set the DIP switch bank (SW3) to match the SW3 DIP Switch Settings table.

    In the following table, up and down indicates the position of the switch with the board orientation as shown in the Switch Locations and Default Settings for Power Solution 2 figure.

    Important: The default MSEL pin settings are set to all zeroes (ON) to select the fast passive parallel x16 mode. For power-up configuration from MAX V and CFI flash, ensure that the MAX® V design uses this same mode as does in the design in the cycloneVSX_5csxfc6df31_soc\examples\max5 directory.
    Table 4.  SW3 DIP Switch Settings
    Switch Board Label Function Default Position
    1 MSEL0 Switch 1 has the following options:
    • ON (up)—MSEL0 is 0.
    • OFF (down)—MSEL0 is 1.
    		ON
    2 MSEL1 Switch 2 has the following options:
    • ON (up)—MSEL1 is 0.
    • OFF (down)—MSEL1 is 1.
    		ON
    3 MSEL2 Switch 3 has the following options:
    • ON (up)—MSEL2 is 0.
    • OFF (down)—MSEL2 is 1.
    		ON
    4 MSEL3 Switch 4 has the following options:
    • ON (up)—MSEL3 is 0.
    • OFF (down)—MSEL3 is 1.
    		ON
    5 MSEL4 Switch 5 has the following options:
    • ON (up)—MSEL4 is 0.
    • OFF (down)—MSEL4 is 1.
    		ON
  3. Set the DIP switch bank (SW4) to match the SW4 JTAG DIP Switch Settings table.

    In the following table, up and down indicates the position of the switch with the board orientation as shown in the Switch Locations and Default Settings for Power Solution 2 figure.

    Table 5.  SW4 JTAG DIP Switch Settings
    Switch Board Label Function Default Position
    1 HPS
    • ON (up)—Do not include HPS in the JTAG chain.
    • OFF (down)—Include HPS in the JTAG chain.
    		OFF
    2 FPGA
    • ON (up)—Do not include the FPGA in the JTAG chain.
    • OFF (down)—Include the FPGA in the JTAG chain.
    		OFF
    3 HSMC
    • ON (up)—Do not include the HSMC connector in the JTAG chain.
    • OFF (down)—Include the HSMC connector in the JTAG chain.
    		ON
    4 MAX
    • ON (up)—Do not include the MAX® V system controller in the JTAG chain.
    • OFF (down)—Include the MAX® V system controller in the JTAG chain.
    		OFF
  4. Set the DIP switch bank (SW6) to match the SW6 JTAG DIP Switch Settings table.

    In the following table, up and down indicates the position of the switch with the board orientation as shown in the Switch Locations and Default Settings for Power Solution 2 figure.

    Table 6.  SW6 JTAG DIP Switch Settings
    Switch Board Label Function Default Position
    1 I2C_SDA_HPS
    • ON (down)—Include HPS in the JTAG chain.
    • OFF (up)—Do not include HPS in the JTAG chain.
    		ON
    2 I2C_SCL_HPS
    • ON (down)—Include HPS in the JTAG chain.
    • OFF (up)—Do not include HPS in the JTAG chain.
    		ON
    3

    I2C_SCL
    • ON (down)—Include the FPGA in the JTAG chain.
    • OFF (up)—Do not include the FPGA in the JTAG chain.
    		ON
    4 I2C_SDA
    • ON (down)—Include the FPGA in the JTAG chain.
    • OFF (up)—Do not include the FPGA in the JTAG chain.
    		ON
  5. Set the following jumper blocks to match the Default Jumper Settings for Power Solution 2 Board table and the Switch Locations and Default Settings for Power Solution 2 Board figure.
    Table 7.  Default Jumper Settings for Power Solution 2 Board
    Switch Board Label Function Default Position
    J6 JTAG HPS SEL
    • SHORT—Controls the HPS from the onboard Intel® FPGA Download Cable II JTAG master.
    • OPEN—Controls the HPS from Mictor-based JTAG master, such as DSTREAM* or Lauterbach* programming cables. Also, set SW4.1 to ON to remove the onboard Intel® FPGA Download Cable II from driving the HPS JTAG input port in this mode.
    		SHORT
    J7 JTAG SEL
    • SHORT—The Intel® FPGA Download Cable II is the source of the JTAG chain.
    • OPEN—The Mictor is the source of the JTAG chain.
    		 SHORT
    J13 OSC1_CLK_SEL
    • SHORT—Selects the onboard 25 MHz clock.
    • OPEN—Selects SMA.
    		 SHORT
    J16 JTAG MIC SEL
    • SHORT—JTAG TRST input to HPS driven from the JTAG chain.
    • OPEN—JTAG TRST input to HPS driven from the Mictor.
    		 OPEN
    J26 CLKSEL0 Selects the HPS clock settings. 1 SHORT pins 2-3
    J27 CLKSEL1 Selects the HPS clock settings.1 SHORT pins 2-3
    J28 BOOTSEL0 Selects the boot mode and source for the HPS.1 SHORT pins 1-2
    J29 BOOTSEL1 Selects the boot mode and source for the HPS.1 SHORT pins 2-3
    J30 BOOTSEL2 Selects the boot mode and source for the HPS.1 SHORT pins 1-2
    J31 SPI I2C
    • SHORT—Select SPI bus access from HPS to Linear Tech daughter card interface through J32.
    • OPEN—Select I2C bus access from HPS to Linear Tech daughter card interface through J32. 2
    		OPEN
    J39 —
    • SHORT—External Mictor 38-pin connector's pin 14 is powered by 3.3 V rail.
    • OPEN—External Mictor 38-pin connector's pin 14 is floating.
    		 SHORT
Related Information
1 For more information, refer to the Cyclone® V Device Handbook Volume 1: Device Interfaces and Integration.
2 This connection can be software controlled from the HPS GPIO pin F16 on rev D and later boards.
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