Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813671
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 5 Clocking and PLL Overview 2. Agilex™ 5 Clocking and PLL Architecture and Features 3. Agilex™ 5 Clocking and PLL Design Considerations 4. Clock Control Intel® FPGA IP Core 5. IOPLL Intel® FPGA IP Core 6. I/O PLL Reconfiguration 7. Document Revision History for the Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs
1. Agilex™ 5 Clocking and PLL Overview x
1.1. Clock Networks Overview 1.2. PLLs Overview
2. Agilex™ 5 Clocking and PLL Architecture and Features x
2.1. Clock Networks Architecture and Features 2.2. PLLs Architecture and Features
2.1. Clock Networks Architecture and Features x
2.1.1. Clock Network Architecture 2.1.2. Clock Resources 2.1.3. Clock Control Features
2.1.1. Clock Network Architecture x
2.1.1.1. Clock Network Hierarchy 2.1.1.2. Clock Sectors 2.1.1.3. Programmable Clock Routing
2.1.3. Clock Control Features x
2.1.3.1. Clock Gating 2.1.3.2. Clock Divider
2.1.3.1. Clock Gating x
2.1.3.1.1. Root Clock Gate 2.1.3.1.2. Sector Clock Gate 2.1.3.1.3. I/O PLL Clock Gate 2.1.3.1.4. LAB Clock Gate
2.2. PLLs Architecture and Features x
2.2.1. PLL Features 2.2.2. PLL Usage 2.2.3. PLL Locations 2.2.4. PLL Architecture 2.2.5. PLL Control Signals 2.2.6. PLL Feedback Modes 2.2.7. Clock Multiplication and Division 2.2.8. Programmable Phase Shift 2.2.9. Programmable Duty Cycle 2.2.10. PLL Cascading 2.2.11. PLL Input Clock Switchover 2.2.12. PLL Reconfiguration and Dynamic Phase Shift 2.2.13. PLL Calibration
2.2.5. PLL Control Signals x
2.2.5.1. Reset 2.2.5.2. Locked
2.2.6. PLL Feedback Modes x
2.2.6.1. Direct Compensation Mode 2.2.6.2. LVDS Compensation Mode 2.2.6.3. Source Synchronous Compensation Mode 2.2.6.4. Normal Compensation Mode 2.2.6.5. Zero-Delay Buffer Mode 2.2.6.6. External Feedback Mode
2.2.11. PLL Input Clock Switchover x
2.2.11.1. Automatic Switchover 2.2.11.2. Automatic Switchover with Manual Override 2.2.11.3. Manual Clock Switchover
2.2.13. PLL Calibration x
2.2.13.1. Power-Up Calibration 2.2.13.2. User Calibration 2.2.13.3. Static Phase Error Calibration
3. Agilex™ 5 Clocking and PLL Design Considerations x
3.1. Guidelines: Clock Switchover 3.2. Guidelines: Timing Closure 3.3. Guidelines: Resetting the PLL 3.4. Guidelines: Configuration Constraints 3.5. Clocking Constraints 3.6. IP Core Constraints 3.7. Guideline: Achieving 5% Duty Cycle for fOUT_EXT ≥ 300 MHz Using tx_outclk Port from LVDS SERDES Intel® FPGA IP
4. Clock Control Intel® FPGA IP Core x
4.1. Release Information for Clock Control Intel® FPGA IP 4.2. Clock Control IP Core Parameters 4.3. Clock Control IP Core Ports and Signals
5. IOPLL Intel® FPGA IP Core x
5.1. Release Information for IOPLL Intel® FPGA IP Core 5.2. IOPLL IP Core Parameters 5.3. IOPLL IP Core Ports and Signals
5.2. IOPLL IP Core Parameters x
5.2.1. IOPLL IP Core Parameters - PLL Tab 5.2.2. IOPLL IP Core Parameters - Settings Tab 5.2.3. IOPLL IP Core Parameters - Cascading Tab 5.2.4. IOPLL IP Core Parameters - Advanced Parameters Tab
6. I/O PLL Reconfiguration x
6.1. Release Information for EMIF Calibration IP 6.2. Implementing HSIO I/O PLL Reconfiguration using EMIF Calibration IP 6.3. Implementing HVIO I/O PLL Reconfiguration 6.4. Reconfiguration Guideline for I/O PLLs 6.5. Axilite Interface Ports in the EMIF Calibration IP 6.6. Address Bus and Data Bus Settings 6.7. Design Example
6.2. Implementing HSIO I/O PLL Reconfiguration using EMIF Calibration IP x
6.2.1. Setting Up the IOPLL Intel® FPGA IP 6.2.2. Setting Up the EMIF Calibration IP 6.2.3. Connectivity Between IOPLL and EMIF Calibration IP
6.3. Implementing HVIO I/O PLL Reconfiguration x
6.3.1. Setting Up the IOPLL Intel® FPGA IP 6.3.2. Read and Write Operations
6.4. Reconfiguration Guideline for I/O PLLs x
6.4.1. Enabling Reconfiguration for The Desired I/O PLL 6.4.2. Clearing off Calibration Statuses 6.4.3. Reconfiguring The I/O PLL 6.4.4. Recalibration of I/O PLL 6.4.5. Clock Gating (Optional)
6.6. Address Bus and Data Bus Settings x
6.6.1. Divide Settings and the Corresponding Data Bit Setting for Reconfiguration 6.6.2. Data Bus Setting for Clock Gating Reconfiguration 6.6.3. Data Bus Setting For Charge Pump Current
6.7. Design Example x
6.7.1. Reconfiguration Option: Reconfiguration Through EMIF Calibration IP 6.7.2. Reconfiguration Option: Reconfiguration Through HVIO Interfaces 6.7.3. Reconfiguration Option: Clock Gating Reconfiguration
1. Agilex™ 5 Clocking and PLL Overview
2. Agilex™ 5 Clocking and PLL Architecture and Features
3. Agilex™ 5 Clocking and PLL Design Considerations
4. Clock Control Intel® FPGA IP Core
5. IOPLL Intel® FPGA IP Core
6. I/O PLL Reconfiguration
7. Document Revision History for the Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs

4.2. Clock Control IP Core Parameters

Table 5.   Clock Control IP Core Parameters for Agilex™ 5 Devices
Parameter Value Description
Number of Clock Inputs 1, 2, or 4

Specify the number of input clock sources for the clock control block. You can specify up to four clock inputs.

Clock multiplexing in Agilex™ 5 devices is implemented using soft logic in the core.

Ensure glitch free clock switchover On or Off

Turn on this option to implement a glitch-free switchover in soft logic when you use multiple clock inputs. You must ensure the currently selected clock is running before switching to another source.

If the selected clock is not running, you cannot switch to the new clock source using the glitch-free switchover implementation.

The clkselect port is initially configured as 00 by default. To activate the clkselect ports and drive the clock network, a clock signal must be provided to inclk0x.

Turning off this option implements a simple multiplexer logic. For more information about optimal clock multiplexing design, refer to Clock Multiplexing in the Quartus® Prime Pro Edition: Design Recommendations.

Clock Enable On or Off Turn on this option if you want to gate your clock output with an enable signal. This option disables the option to use clock division.
Clock Enable Type Root Level or Distributed Sector Level Select the clock gates located in the periphery or the gates located in the sector. For more information about the clock gates, refer to the Clock Gating section.
Enable Register Mode Negative Latch or None Specify if the enable signal should be latched.
Clock Divider On or Off Turn on this option if you want to use the clock division block in the periphery.

This option disables the option to use clock enable.
Clock Divider Output Ports Divide 1x, Divide 1x and 2x, or Divide 1x, 2x and 4x Specify the combination of passing your clock through, dividing your clock by 2, or dividing your clock by 4.
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