Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs

ID 813671
Date 7/25/2024
Public
Document Table of Contents

6.3.2. Read and Write Operations

Due to the 32-bit data width of the registers, read and write operations to core_avl_readdata[7:0] and core_avl_writedata[7:0] must be split into four separate 8-bit transfers, each spaced by intervals equal to the clock period and processed sequentially from the least significant to the most significant 8-bit segment. When core_avl_read is asserted for a read cycle, the first four 8-bit segments become 0x00 and should be discarded. To ensure synchronization of the read cycle, a 0x00 word is inserted between successive 32-bit register reads. When reading from multiple addresses in one cycle, each address must be held for multiples of 5 clock cycles. All four segments of the 32-bit register, along with the 0x00 word, are returned before proceeding to the next address. Holding addresses for non-multiples of 5 clock cycles may result in missed or misaligned data.