Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs

ID 813671
Date 10/07/2024
Public
Document Table of Contents

6.2.1. Setting Up the IOPLL Intel® FPGA IP

Figure 26. IOPLL Intel® FPGA IP
  1. At the dynamic reconfiguration tab, enable dynamic reconfiguration of PLL using calibration IP.
  2. Set the respective base address for the I/O PLL desired to be configured from 0 to 255. You cannot share the same base address if you use more than one PLL in the design. For instance, If PLL 1 Base address is assigned to d’20. Then, the next closest address that can be assigned for PLL2 is d’40, and for PLL3 is d’60. Quartus® Prime reads the base address and knows which PLL on the chip to reconfigure.
    Note: I/O bank cannot simultaneously support a PLL running dynamic reconfiguration and an EMIF.