Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813665
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10M/100M/1G Ethernet Design Example 3. 1G Ethernet Design Example with IEEE 1588v2 Feature 4. 2.5G Ethernet Design Example 5. 2.5G Ethernet Design Example with IEEE 1588v2 Feature 6. 10G Ethernet Design Example 7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example 8. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588 Design Example 9. Interface Signals Description 10. Configuration Registers Description 11. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives 12. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Configuring the Design Example in Hardware 1.5. Signal Tap Debugging
1.2. Generating the Design x
1.2.1. Procedure 1.2.2. Design Example Parameters
1.3. Simulating the Design x
1.3.1. Procedure 1.3.2. Testbench
1.4. Compiling and Configuring the Design Example in Hardware x
1.4.1. Procedure 1.4.2. Hardware Setup
1.5. Signal Tap Debugging x
1.5.1. Signal Tap Debug Signals
2. 10M/100M/1G Ethernet Design Example x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signals 2.7. Configuration Registers
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme 2.3.3. Reset Scheme
2.5. Hardware Testing x
2.5.1. Test Procedure
2.7. Configuration Registers x
2.7.1. Packet Generator and Traffic Monitor Register Map
3. 1G Ethernet Design Example with IEEE 1588v2 Feature x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing 3.6. Interface Signals 3.7. Configuration Registers
3.3. Functional Description x
3.3.1. Design Components 3.3.2. Clocking Scheme 3.3.3. Reset Scheme
3.4. Simulation x
3.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
3.5. Hardware Testing x
3.5.1. Test Procedure
4. 2.5G Ethernet Design Example x
4.1. Features 4.2. Hardware and Software Requirements 4.3. Functional Description 4.4. Simulation 4.5. Hardware Testing 4.6. Interface Signals 4.7. Configuration Registers
4.3. Functional Description x
4.3.1. Design Components 4.3.2. Clocking Scheme 4.3.3. Reset Scheme
4.5. Hardware Testing x
4.5.1. Test Procedure
4.7. Configuration Registers x
4.7.1. Packet Generator and Traffic Monitor Register Map
5. 2.5G Ethernet Design Example with IEEE 1588v2 Feature x
5.1. Features 5.2. Hardware and Software Requirements 5.3. Functional Description 5.4. Simulation 5.5. Hardware Testing 5.6. Interface Signals 5.7. Configuration Registers
5.3. Functional Description x
5.3.1. Design Components 5.3.2. Clocking Scheme 5.3.3. Reset Scheme
5.4. Simulation x
5.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
5.5. Hardware Testing x
5.5.1. Test Procedure
6. 10G Ethernet Design Example x
6.1. Features 6.2. Hardware and Software Requirements 6.3. Functional Description 6.4. Simulation 6.5. Interface Signals 6.6. Configuration Registers
6.3. Functional Description x
6.3.1. Design Components 6.3.2. Clocking Scheme 6.3.3. Reset Scheme
6.6. Configuration Registers x
6.6.1. Packet Generator and Traffic Monitor Register Map
7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example x
7.1. Features 7.2. Hardware and Software Requirements 7.3. Functional Description 7.4. Simulation 7.5. Hardware Testing 7.6. Interface Signals 7.7. Configuration Registers
7.3. Functional Description x
7.3.1. Design Components 7.3.2. Clocking Scheme 7.3.3. Reset Scheme
7.5. Hardware Testing x
7.5.1. Test Procedure
7.7. Configuration Registers x
7.7.1. Packet Generator and Traffic Monitor Register Map
8. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588 Design Example x
8.1. Features 8.2. Hardware and Software Requirements 8.3. Functional Description 8.4. Simulation 8.5. Hardware Testing 8.6. Interface Signals
8.3. Functional Description x
8.3.1. Design Components 8.3.2. Clocking Scheme 8.3.3. Reset Scheme
8.4. Simulation x
8.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
8.5. Hardware Testing x
8.5.1. Test Procedure
9. Interface Signals Description x
9.1. Clock and Reset Interface Signals 9.2. Avalon® Memory-Mapped Interface Signals 9.3. Avalon® Streaming Interface Signals 9.4. PHY Interface Signals 9.5. Status Interface 9.6. IEEE 1588v2 Timestamp Interface Signals
10. Configuration Registers Description x
10.1. Register Access Definition 10.2. Low Latency Ethernet 10G MAC 10.3. PHY
10.3. PHY x
10.3.1. 1G/2.5G/5G/10G Multirate PHY
1. Quick Start Guide
2. 10M/100M/1G Ethernet Design Example
3. 1G Ethernet Design Example with IEEE 1588v2 Feature
4. 2.5G Ethernet Design Example
5. 2.5G Ethernet Design Example with IEEE 1588v2 Feature
6. 10G Ethernet Design Example
7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
8. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588 Design Example
9. Interface Signals Description
10. Configuration Registers Description
11. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
12. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

10.2. Low Latency Ethernet 10G MAC

This topic lists the byte offsets the MAC registers.

Table 39.  Primary MAC Address
Byte Offset R/W Name HW Reset
0x2008 RW primary_mac_addr0 0x0
0x200C RW primary_mac_addr1 0x0
Table 40.  TX Configuration and Status Registers
Byte Offset R/W Name HW Reset
0x4000 RW tx_packet_control 0x0
0x4004 RO tx_packet_status 0x0
0x4100 RW tx_pad_control 0x1
0x4200 RW tx_crc_control 0x3
0x4400

—

Reserved

—
0x6004 RW tx_frame_maxlength 0x5EE(1518)
0x4300 RO tx_underflow_counter0 0x0
0x4304 RO tx_underflow_counter1 0x0
Table 41.  Flow Control Registers
Byte Offset R/W Name HW Reset
0x4500 RW tx_pauseframe_control 0x0
0x4504 RW tx_pauseframe_quanta 0x0
0x4508 RW tx_pauseframe_enable 0x1
Table 42.  RX Configuration and Status Registers
Byte Offset R/W Name HW Reset
0x0000 RW rx_transfer_control 0x0
0x0004 RO rx_transfer_status 0x0
0x0100 RW rx_padcrc_control 0x1
0x0200 RW rx_crccheck_control 0x2
0x0400 RW rx_custom_preamble_forward 0x0
0x0500

—

Reserved

—
0x2000 RW rx_frame_control 0x3
0x2004 RW rx_frame_maxlength 0x5EE(1518)
0x2010 RW rx_frame_spaddr0_0 0x0
0x2014 RW rx_frame_spaddr0_1 0x0
0x2018 RW rx_frame_spaddr1_0 0x0
0x201C RW rx_frame_spaddr1_1 0x0
0x2020 RW rx_frame_spaddr2_0 0x0
0x2024 RW rx_frame_spaddr2_1 0x0
0x2028 RW rx_frame_spaddr3_0 0x0
0x202C RW rx_frame_spaddr3_1 0x0
0x2060

—

Reserved

—
0x0300 RO rx_pktovrflow_error 0x0
Table 43.  TX and RX Statistics Registers
Byte Offset R/W Name HW Reset
0x7000 RO tx_stats_clr 0x0
0x3000 RO rx_stats_clr 0x0
0x7008:0x700C RO tx_stats_framesOK 0x0
0x3008:0x300C RO rx_stats_framesOK 0x0
0x7010:0x7014 RO tx_stats_framesErr 0x0
0x3010:0x3014 RO rx_stats_framesErr 0x0
0x7018:0x701C RO tx_stats_framesCRCErr 0x0
0x3018:0x301C RO rx_stats_framesCRCErr 0x0
0x7020:0x7024 RO tx_stats_octetsOK 0x0
0x3020:0x3024 RO rx_stats_octetsOK 0x0
0x7028:0x702C RO tx_stats_pauseMACCtrl_Frames 0x0
0x3028:0x302C RO rx_stats_pauseMACCtrl_Frames 0x0
0x7030:0x7034 RO tx_stats_ifErrors 0x0
0x3030:0x3034 RO rx_stats_ifErrors 0x0
0x7038:0x703C RO tx_stats_unicast_FramesOK 0x0
0x3038:0x303C RO rx_stats_unicast_FramesOK 0x0
0x7040:0x7044 RO tx_stats_unicast_FramesErr 0x0
0x3040:0x3044 RO rx_stats_unicast_FramesErr 0x0
0x7048:0x704C RO tx_stats_multicast_FramesOK 0x0
0x3048:0x304C RO rx_stats_multicast_FramesOK 0x0
0x7050:0x7054 RO tx_stats_multicast_FramesErr 0x0
0x3050:0x3054 RO rx_stats_multicast_FramesErr 0x0
0x7058:0x705C RO tx_stats_broadcast_FramesOK 0x0
0x3058:0x305C RO rx_stats_broadcast_FramesOK 0x0
0x7060:0x7064 RO tx_stats_broadcast_FramesErr 0x0
0x3060:0x3064 RO rx_stats_broadcast_FramesErr 0x0
0x7068:0x706C RO tx_stats_etherStatsOctets 0x0
0x3068:0x306C RO rx_stats_etherStatsOctets 0x0
0x7070:0x7074 RO tx_stats_etherStatsPkts 0x0
0x3070:0x3074 RO rx_stats_etherStatsPkts 0x0
0x7078:0x707C RO tx_stats_etherStatsUndersizePkts 0x0
0x3078:0x307C RO rx_stats_etherStatsUndersizePkts 0x0
0x7080:0x7084 RO tx_stats_etherStatsOversizePkts 0x0
0x3080:0x3084 RO rx_stats_etherStatsOversizePkts 0x0
0x7088:0x708C RO tx_stats_etherStatsPkts64Octets 0x0
0x3088:0x308C RO rx_stats_etherStatsPkts64Octets 0x0
0x7090:0x7094 RO tx_stats_etherStatsPkts65to127Octets 0x0
0x3090:0x3094 RO rx_stats_etherStatsPkts65to127Octets 0x0
0x7098:0x709C RO tx_stats_etherStatsPkts128to255Octets 0x0
0x3098:0x309C RO rx_stats_etherStatsPkts128to255Octets 0x0
0x70A0:0x70A4 RO tx_stats_etherStatsPkts256to511Octets 0x0
0x30A0:0x30A4 RO rx_stats_etherStatsPkts256to511Octets 0x0
0x70A8:0x70AC RO tx_stats_etherStatsPkts512to1023Octets 0x0
0x30A8:0x30AC RO rx_stats_etherStatsPkts512to1023Octets 0x0
0x70B0:0x70B4 RO tx_stats_etherStatPkts1024to1518Octets 0x0
0x30B0:0x30B4 RO rx_stats_etherStatPkts1024to1518Octets 0x0
0x70B8:0x70BC RO tx_stats_etherStatsPkts1519toXOctets 0x0
0x30B8:0x30BC RO rx_stats_etherStatsPkts1519toXOctets 0x0
0x70C0:0x70C4 RO tx_stats_etherStatsFragments 0x0
0x30C0:0x30C4 RO rx_stats_etherStatsFragments 0x0
0x70C8:0x70CC RO tx_stats_etherStatsJabbers 0x0
0x30C8:0x30CC RO rx_stats_etherStatsJabbers 0x0
0x70D0:0x70D4 RO tx_stats_etherStatsCRCErr 0x0
0x30D0:0x30D4 RO rx_stats_etherStatsCRCErr 0x0
0x70D8:0x70DC RO tx_stats_unicastMACCtrlFrames 0x0
0x30D8:0x30DC RO rx_stats_unicastMACCtrlFrames 0x0
0x70E0:0x70E4 RO tx_stats_multicastMACCtrlFrames 0x0
0x30E0:0x30E4 RO rx_stats_multicastMACCtrlFrames 0x0
0x70E8:0x70EC RO tx_stats_broadcastMACCtrlFrames 0x0
0x30E8:0x30EC RO rx_stats_broadcastMACCtrlFrames 0x0
0x70F0:0x70F4 RO tx_stats_PFCMACCtrlFrames 0x0
0x30F0:0x30F4 RO rx_stats_PFCMACCtrlFrames 0x0
Level Two Title