Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813665
Date 10/07/2024
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10M/100M/1G Ethernet Design Example 3. 1G Ethernet Design Example with IEEE 1588v2 Feature 4. 2.5G Ethernet Design Example 5. 2.5G Ethernet Design Example with IEEE 1588v2 Feature 6. 10G Ethernet Design Example 7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example 8. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588 Design Example 9. Interface Signals Description 10. Configuration Registers Description 11. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives 12. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Configuring the Design Example in Hardware 1.5. Signal Tap Debugging
1.2. Generating the Design x
1.2.1. Procedure 1.2.2. Design Example Parameters
1.3. Simulating the Design x
1.3.1. Procedure 1.3.2. Testbench
1.4. Compiling and Configuring the Design Example in Hardware x
1.4.1. Procedure 1.4.2. Hardware Setup
1.5. Signal Tap Debugging x
1.5.1. Signal Tap Debug Signals
2. 10M/100M/1G Ethernet Design Example x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signals 2.7. Configuration Registers
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme 2.3.3. Reset Scheme
2.5. Hardware Testing x
2.5.1. Test Procedure
2.7. Configuration Registers x
2.7.1. Packet Generator and Traffic Monitor Register Map
3. 1G Ethernet Design Example with IEEE 1588v2 Feature x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing 3.6. Interface Signals 3.7. Configuration Registers
3.3. Functional Description x
3.3.1. Design Components 3.3.2. Clocking Scheme 3.3.3. Reset Scheme
3.4. Simulation x
3.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
3.5. Hardware Testing x
3.5.1. Test Procedure
4. 2.5G Ethernet Design Example x
4.1. Features 4.2. Hardware and Software Requirements 4.3. Functional Description 4.4. Simulation 4.5. Hardware Testing 4.6. Interface Signals 4.7. Configuration Registers
4.3. Functional Description x
4.3.1. Design Components 4.3.2. Clocking Scheme 4.3.3. Reset Scheme
4.5. Hardware Testing x
4.5.1. Test Procedure
4.7. Configuration Registers x
4.7.1. Packet Generator and Traffic Monitor Register Map
5. 2.5G Ethernet Design Example with IEEE 1588v2 Feature x
5.1. Features 5.2. Hardware and Software Requirements 5.3. Functional Description 5.4. Simulation 5.5. Hardware Testing 5.6. Interface Signals 5.7. Configuration Registers
5.3. Functional Description x
5.3.1. Design Components 5.3.2. Clocking Scheme 5.3.3. Reset Scheme
5.4. Simulation x
5.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
5.5. Hardware Testing x
5.5.1. Test Procedure
6. 10G Ethernet Design Example x
6.1. Features 6.2. Hardware and Software Requirements 6.3. Functional Description 6.4. Simulation 6.5. Interface Signals 6.6. Configuration Registers
6.3. Functional Description x
6.3.1. Design Components 6.3.2. Clocking Scheme 6.3.3. Reset Scheme
6.6. Configuration Registers x
6.6.1. Packet Generator and Traffic Monitor Register Map
7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example x
7.1. Features 7.2. Hardware and Software Requirements 7.3. Functional Description 7.4. Simulation 7.5. Hardware Testing 7.6. Interface Signals 7.7. Configuration Registers
7.3. Functional Description x
7.3.1. Design Components 7.3.2. Clocking Scheme 7.3.3. Reset Scheme
7.5. Hardware Testing x
7.5.1. Test Procedure
7.7. Configuration Registers x
7.7.1. Packet Generator and Traffic Monitor Register Map
8. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588 Design Example x
8.1. Features 8.2. Hardware and Software Requirements 8.3. Functional Description 8.4. Simulation 8.5. Hardware Testing 8.6. Interface Signals
8.3. Functional Description x
8.3.1. Design Components 8.3.2. Clocking Scheme 8.3.3. Reset Scheme
8.4. Simulation x
8.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
8.5. Hardware Testing x
8.5.1. Test Procedure
9. Interface Signals Description x
9.1. Clock and Reset Interface Signals 9.2. Avalon® Memory-Mapped Interface Signals 9.3. Avalon® Streaming Interface Signals 9.4. PHY Interface Signals 9.5. Status Interface 9.6. IEEE 1588v2 Timestamp Interface Signals
10. Configuration Registers Description x
10.1. Register Access Definition 10.2. Low Latency Ethernet 10G MAC 10.3. PHY
10.3. PHY x
10.3.1. 1G/2.5G/5G/10G Multirate PHY Register Map Register Definitions
1. Quick Start Guide
2. 10M/100M/1G Ethernet Design Example
3. 1G Ethernet Design Example with IEEE 1588v2 Feature
4. 2.5G Ethernet Design Example
5. 2.5G Ethernet Design Example with IEEE 1588v2 Feature
6. 10G Ethernet Design Example
7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
8. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588 Design Example
9. Interface Signals Description
10. Configuration Registers Description
11. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
12. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

10.3.1. 1G/2.5G/5G/10G Multirate PHY

This topic lists the byte offsets of the 1G/2.5G/5G/10G Multirate variant registers for Agilex™ 5 devices.

Register Map

You can access the 16-bit/32-bit configuration registers via the Avalon® memory-mapped interface.

Table 44.  Register Map Overview
Address Range Usage Register Width Configuration
0x00 : 0x1F 1000BASE-X/SGMII 16 2.5G, 1G/2.5G, 10M/100M/1G/2.5G, 10M/100M/1G/2.5G/10G, 1G/2.5G/10G

0x400 : 0x43F

 USXGMII 32

10M/100M/1G/2.5G/5G/10G (USXGMII)

Register Definitions

Observe the following guidelines when accessing the registers:
  • Do not write to reserved or undefined registers.
  • When writing to the registers, perform read-modify-write operation to ensure that reserved or undefined register bits are not overwritten.
Table 45.  1G/2.5G/5G/10G Multirate PHY Register Definitions
Word Offset Name Description Access HW Reset Value
0x00 control Bit [15]: RESET. Set this bit to 1 to trigger a soft reset.

The PHY clears the bit when the reset is completed. The register values remain intact during the reset.

 RWC 0
Bit[14]: Reserved. — —
Bit [12]: AUTO_NEGOTIATION_ENABLE. Set this bit to 1 to enable auto-negotiation.

Auto-negotiation is supported only in 1GbE. Therefore, set this bit to 0 when you switch to a speed other than 1GbE.

 RW 0
Bit [9]: RESTART_AUTO_NEGOTIATION. Set this bit to 1 to restart auto-negotiation.

The PHY clears the bit as soon as auto-negotiation is restarted.

 RWC 0
All other bits are reserved. — —
0x01 status Bit [5]: AUTO_NEGOTIATION_COMPLETE. A value of "1" indicates that the auto-negotiation is completed. RO 0
Bit [3]: AUTO_NEGOTIATION_ABILITY. A value of "1" indicates that the PCS function supports auto-negotiation. RO 1
Bit [2]: LINK_STATUS. A value of "0" indicates that the link is lost. A value of "1" indicates that the link is established. RO 0
All other bits are reserved. — —
0x02:0x03 phy_identifier The value set in the PHY_IDENTIFIER parameter. RO Value of PHY_IDENTIFIER parameter
0x04 dev_ability Use this register to advertise the device abilities during auto-negotiation. — —
Bits [13:12]: RF. Specify the remote fault.
  • 00: No error.
  • 01: Link failure.
  • 10: Off-line.
  • 11: Auto-negotiation error.
 RW 00
Bits [8:7]: PS. Specify the PAUSE support.
  • 00: No PAUSE.
  • 01: Symmetric PAUSE.
  • 10: Asymmetric PAUSE towards the link partner.
  • 11: Asymmetric and symmetric PAUSE towards the link device.
RW 11
Bit [5]: FD. Ensure that this bit is always set to 1. RW 1
All other bits are reserved. — —
0x05 (1000BASE-X mode) partner_ability The device abilities of the link partner during auto-negotiation. — —
Bit [14]: ACK. A value of "1" indicates that the link partner has received three consecutive matching ability values from the device. RO 0
Bits [13:12]: RF. The remote fault.
  • 00: No error.
  • 01: Link failure.
  • 10: Off-line.
  • 11: Auto-negotiation error.
 RO 0
Bits [8:7]: PS. The PAUSE support.
  • 00: No PAUSE.
  • 01: Symmetric PAUSE.
  • 10: Asymmetric PAUSE towards the link partner.
  • 11: Asymmetric and symmetric PAUSE towards the link device.
 RO 0
Bit [6]: HD. A value of "1" indicates that half-duplex is supported. RO 0
Bit [5]: FD. A value of "1" indicates that full-duplex is supported. RO 0
All other bits are reserved. — —
0x05 (SGMII mode) partner_ability The device abilities of the link partner during auto-negotiation. — —
Bit [11:10]: COPPER_SPEED
Link partner speed:
  • 00: copper interface speed is 10 Mbps
  • 01: copper interface speed is 100 Mbps
  • 10: copper interface speed is 1 Gigabit
  • 11: reserved
 RO 00
Bit [12]: COPPER_DUPLEX_STATUS
Link partner capability:
  • 1: copper interface is capable of full-duplex operation
  • 0: copper interface is capable of half-duplex operation
 RO 0
Bit [14]: ACK. Link partner acknowledge. A value of 1 indicates that the device received three consecutive matching ability values from its link partner. RO 0
Bit [15]: COPPER_LINK_STATUS
Link partner status:
  • 1: copper interface link is up
  • 0: copper interface link is down
 RO 0
All other bits are reserved. — —
0x06 an_expansion The PCS capabilities and auto-negotiation status. — —
Bit [1]: PAGE_RECEIVE. A value of "1" indicates that the partner_ability register has been updated. This bit is automatically cleared once it is read. RO 0
Bit [0]: LINK_PARTNER_AUTO_NEGOTIATION_ABLE. A value of "1" indicates that the link partner supports auto-negotiation. RO 0
0x07 device_next_page The PHY does not support the next page feature. These registers are always set to 0. RO 0
0x08 partner_next_page RO 0
0x09:0x0F Reserved — — —

0x10

 scratch Provides a memory location to test read and write operations.

RW

 0
Bit [31:16]: Reserved — —
0x11 rev The current version of the PHY IP. RO Current version of the PHY
Bit [31:16]: Reserved — —
0x12:0x13 link_timer
21-bit auto-negotiation link timer. Set the link timer value from 0 to 16 ms in 16 ns steps (62.5 MHz clock periods for 1G). The reset value sets the link timer to ~10 ms (10,002,432 ns).
  • Bit [15:0] are written to word offset 0x12. Bit [8:0] of word offset 0x12 is always set to 0. Any value written to it is ignored.
  • Bit [20:16] are written to word offset 0x13. The remaining bits are reserved and always set to 0. Since bit [8:0] is always set to 0, the highest resolution for 1G is 8192 ns.
RW

[20:9] 0x4C5 [8:0] 0x0

OR

Addr 0x13: [20:16] 0x9 Addr 0x12: [15:0] 0x8A00
0x14 if_mode Interface Mode Register — —
Bit [0]: SGMII_ENA

Determines the PCS function operating mode. Setting this bit to 1b'1 enables SGMII mode. Setting this bit to 1b'0 enables 1000BASE-X gigabit mode.

RW 0
Bit [1]: USE_SGMII_AN

In SGMII mode, setting this bit to 1b'1 configures the PCS with the link partner abilities advertised during auto-negotiation. If this bit is set to 1b'0, the PCS function should be configured with the SGMII_SPEED bits.

RW 0
Bit [3:2]: SGMII_SPEED
When the PCS operates in SGMII mode (SGMII_ENA = 1) and is not programmed for automatic configuration (USE_SGMII_AN = 0), the following encodings specify the speed:
  • 2'b00: 10 Mbps
  • 2'b01: 100 Mbps
  • 2'b10: Gigabit
  • 2'b11: Reserved
These bits are not used when SGMII_ENA = 0 or USE_SGMII_AN = 1.
RW 0
All other bits are reserved. — —
0x15 Reserved — — —
0x17 dl_ctrl Bit [0]: tx_measure_valid
Indicates whether the TX deterministic latency measurement values are valid
  • 0: Not valid
  • 1: Valid
 RO 0x0
Bit [1]: rx_measure_valid
Indicates whether the RX deterministic latency measurement values are valid.
  • 0: Not valid
  • 1: Valid
 RO 0x0
Bit [2]: tx_dl_reset
TX Deterministic Latency (DL) soft reset. Provides a soft reset to the TX DL block.
  • 0: TX DL block is not under reset
  • 1: TX DL block is being reset
Note: This is not a self-clearing reset.
RW 0x0
Bit [3]: rx_dl_reset
RX Deterministic Latency (DL) soft reset. Provides a soft reset to the RX DL block.
  • 0: RX DL block is not under reset
  • 1: RX DL block is being reset
Note: This is not a self-clearing reset.
RW 0x0
0x19:0x18 tx_delay Bit [20:0]: TX Datapath Latency.
Provides the TX datapath deterministic latency values measured in i_dl_sampling_clk cycles.
  • 0x18
    • Bit [15:8]: Unused.
    • Bit [7:0]: The fractional number of clock cycles.
  • 0x19:
    • Bit [15:13]: Unused.
    • Bit [12:0]: The number of clock cycles.

You must set the measure_valid before taking the measurement.

RO 0x0
0x1B:0x1A rx_delay Bit [20:0]: RX Datapath Latency.
Provides the RX datapath deterministic latency values measured in i_dl_sampling_clk cycles.
  • 0x1A:
    • Bit [15:8]: Unused.
    • Bit [7:0]: The fractional number of clock cycles.
  • 0x1B:
    • Bit [15:13]: Unused.
    • Bit [12:0]: The number of clock cycles.

You must set the measure_valid before taking the measurement.

RO 0x0
0x1D:0x1C tx_soft_pcs_latency Bit [21:0]: TX Soft PCS Datapath Latency.
Provides the latency values measured from GMII input interface to 20-bit parallel output of soft PCS logic.
Note: The value of gmii16b_tx_latency can be read from this register.
  • 0x1C:
    • Bit [15:10]: Unused.
    • Bit [9:0]: The fractional number of clock cycles.
  • 0x1D:
    • Bit [15:12]: Unused.
    • Bit [11:0]: The number of clock cycles.
 RO 0x0
0x1F:0x1E rx_soft_pcs_latency Bit [21:0]: RX Soft PCS Datapath Latency.
Provides the latency values measured from 20-bit parallel output of soft PCS logic to GMII output interface of PHY IP.
Note: The value of gmii16b_rx_latency can be read from this register.
  • 0x1E:
    • Bit [15:10]: Unused.
    • Bit [9:0]: The fractional number of clock cycles.
  • 0x1F:
    • Bit [15:12]: Unused.
    • Bit [11:0]: The number of clock cycles.
 RO 0x0
0x400 usxgmii_control Control Register — —
Bit [0]: USXGMII_ENA:
  • 0: 10GBASE-R mode
  • 1: USXGMII mode
 RW 0
Bit [1]: USXGMII_AN_ENA is used when USXGMII_ENA is set to 1:
  • 0: Disables USXGMII Auto-Negotiation and manually configures the operating speed with the USXGMII_SPEED register.
  • 1: Enables USXGMII Auto-Negotiation, and automatically configures operating speed with link partner ability advertised during USXGMII Auto-Negotiation.
RW 1
Bit [4:2]: USXGMII_SPEED is the operating speed of the PHY in USXGMII mode and USE_USXGMII_AN is set to 0.
  • 3’b000: 10M
  • 3’b001: 100M
  • 3’b010: 1G
  • 3’b011: 10G
  • 3’b100: 2.5G
  • 3’b101: 5G
  • 3’b110: Reserved
  • 3’b111: Reserved
 RW 0
Bit [8:5]: Reserved — —
Bit [9]: RESTART_AUTO_NEGOTIATION

Write 1 to restart Auto-Negotiation sequence The bit is cleared by hardware when Auto-Negotiation is restarted.

 RWC 0
Bit [31:10]: Reserved — —
0x401 usxgmii_status Status Register — —
Bit [1:0]: Reserved — —
Bit [2]: LINK_STATUS indicates link status for USXGMII all speeds
  • 1: Link is established
  • 0: Link synchronization is lost, a 0 is latched
 RO 0
Bit [4:3]: Reserved — —
Bit [5]: AUTO_NEGOTIATION_COMPLETE

A value of 1 indicates the Auto-Negotiation process is completed.

 RO 0
Bit [31:6]: Reserved — —
0x402:0x404 Reserved — — —
0x405 usxgmii_partner_ability Device abilities advertised to the link partner during Auto-Negotiation — —
Bit [6:0]: Reserved — —
Bit [7]: EEE_CLOCK_STOP_CAPABILITY
Indicates whether or not energy efficient Ethernet (EEE) clock stop is supported.
  • 0: Not supported
  • 1: Supported
 RO 0
Bit [8]: EEE_CAPABILITY
Indicates whether or not EEE is supported.
  • 0: Not supported
  • 1: Supported
 RO 0
Bit [11:9]: SPEED
  • 3'b000: 10M
  • 3'b001: 100M
  • 3'b010: 1G
  • 3'b011: 10G
  • 3'b100: 2.5G
  • 3'b101: 5G
  • 3'b110: Reserved
  • 3'b111: Reserved
 RO 0
Bit [12]: DUPLEX
Indicates the duplex mode.
  • 0: Half duplex
  • 1: Full duplex
 RO 0
Bit [13]: Reserved — —
Bit [14]: ACKNOWLEDGE

A value of 1 indicates that the device has received three consecutive matching ability values from its link partner.

 RO 0
Bit [15]: LINK
Indicates the link status.
  • 0: Link down
  • 1: Link up
 RO 0
Bit [31:16]: Reserved — —
0x406:0x411 Reserved — — —
0x412 usxgmii_link_timer

Auto-Negotiation link timer. Sets the link timer value in bit [19:14] from 0 to 2 ms in approximately 0.05-ms steps. You must program the link timer to ensure that it matches the link timer value of the external NBASE-T PHY IP.

The reset value sets the link timer to approximately 1.6 ms.

Bits [13:0] are reserved and always set to 0.

 [19:14]: RW

[13:0]: RO

 [19:14]: 1F

[13:0]: 0
0x413:0x41F Reserved — — —
0x420 ptp_dl Bit [0]: tx_measure_valid
Indicates whether the TX deterministic latency measurement values are valid.
  • 0: Not valid
  • 1: Valid
 RO 0x0
Bit [1]: rx_measure_valid
Indicates whether the RX deterministic latency measurement values are valid.
  • 0: Not valid
  • 1: Valid
 RO 0x0
Bit [2]: tx_dl_reset
TX Deterministic Latency (DL) soft reset. Provides a soft reset to the TX DL block.
  • 0: TX DL block is not under reset
  • 1: TX DL block is being reset
Note: This is not a self-clearing reset.
RW 0x0
Bit [3]: rx_dl_reset
RX Deterministic Latency (DL) soft reset. Provides a soft reset to the RX DL block.
  • 0: RX DL block is not under reset
  • 1: RX DL block is being reset
Note: This is not a self-clearing reset.
RW 0x0
0x421 ptp_dl_tx Bit [20:0]: TX Datapath Latency.
Provides the TX datapath deterministic latency values measured in sampling_clk cycles. Fixed point format Q13.8.
  • Bit [20:8]: The number of clock cycles.
  • Bit [7:0]: The fractional number of clock cycles.

tx_measure_valid (bit 0 of register 0x420) must be asserted before taking the measurement.

RO 0x0
0x422 ptp_dl_rx Bit [20:0]: RX Datapath Latency.
Provides the RX datapath deterministic latency values measured in sampling_clk cycles. Fixed point format Q13.8.
  • Bit [20:8]: The number of clock cycles.
  • Bit [7:0]: The fractional number of clock cycles.

rx_measure_valid (bit 0 of register 0x420) must be asserted before taking the measurement.

RO 0x0
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