Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813665
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10M/100M/1G Ethernet Design Example 3. 1G Ethernet Design Example with IEEE 1588v2 Feature 4. 2.5G Ethernet Design Example 5. 2.5G Ethernet Design Example with IEEE 1588v2 Feature 6. 10G Ethernet Design Example 7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example 8. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588 Design Example 9. Interface Signals Description 10. Configuration Registers Description 11. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives 12. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Configuring the Design Example in Hardware 1.5. Signal Tap Debugging
1.2. Generating the Design x
1.2.1. Procedure 1.2.2. Design Example Parameters
1.3. Simulating the Design x
1.3.1. Procedure 1.3.2. Testbench
1.4. Compiling and Configuring the Design Example in Hardware x
1.4.1. Procedure 1.4.2. Hardware Setup
1.5. Signal Tap Debugging x
1.5.1. Signal Tap Debug Signals
2. 10M/100M/1G Ethernet Design Example x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signals 2.7. Configuration Registers
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme 2.3.3. Reset Scheme
2.5. Hardware Testing x
2.5.1. Test Procedure
2.7. Configuration Registers x
2.7.1. Packet Generator and Traffic Monitor Register Map
3. 1G Ethernet Design Example with IEEE 1588v2 Feature x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing 3.6. Interface Signals 3.7. Configuration Registers
3.3. Functional Description x
3.3.1. Design Components 3.3.2. Clocking Scheme 3.3.3. Reset Scheme
3.4. Simulation x
3.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
3.5. Hardware Testing x
3.5.1. Test Procedure
4. 2.5G Ethernet Design Example x
4.1. Features 4.2. Hardware and Software Requirements 4.3. Functional Description 4.4. Simulation 4.5. Hardware Testing 4.6. Interface Signals 4.7. Configuration Registers
4.3. Functional Description x
4.3.1. Design Components 4.3.2. Clocking Scheme 4.3.3. Reset Scheme
4.5. Hardware Testing x
4.5.1. Test Procedure
4.7. Configuration Registers x
4.7.1. Packet Generator and Traffic Monitor Register Map
5. 2.5G Ethernet Design Example with IEEE 1588v2 Feature x
5.1. Features 5.2. Hardware and Software Requirements 5.3. Functional Description 5.4. Simulation 5.5. Hardware Testing 5.6. Interface Signals 5.7. Configuration Registers
5.3. Functional Description x
5.3.1. Design Components 5.3.2. Clocking Scheme 5.3.3. Reset Scheme
5.4. Simulation x
5.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
5.5. Hardware Testing x
5.5.1. Test Procedure
6. 10G Ethernet Design Example x
6.1. Features 6.2. Hardware and Software Requirements 6.3. Functional Description 6.4. Simulation 6.5. Interface Signals 6.6. Configuration Registers
6.3. Functional Description x
6.3.1. Design Components 6.3.2. Clocking Scheme 6.3.3. Reset Scheme
6.6. Configuration Registers x
6.6.1. Packet Generator and Traffic Monitor Register Map
7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example x
7.1. Features 7.2. Hardware and Software Requirements 7.3. Functional Description 7.4. Simulation 7.5. Hardware Testing 7.6. Interface Signals 7.7. Configuration Registers
7.3. Functional Description x
7.3.1. Design Components 7.3.2. Clocking Scheme 7.3.3. Reset Scheme
7.5. Hardware Testing x
7.5.1. Test Procedure
7.7. Configuration Registers x
7.7.1. Packet Generator and Traffic Monitor Register Map
8. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588 Design Example x
8.1. Features 8.2. Hardware and Software Requirements 8.3. Functional Description 8.4. Simulation 8.5. Hardware Testing 8.6. Interface Signals
8.3. Functional Description x
8.3.1. Design Components 8.3.2. Clocking Scheme 8.3.3. Reset Scheme
8.4. Simulation x
8.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
8.5. Hardware Testing x
8.5.1. Test Procedure
9. Interface Signals Description x
9.1. Clock and Reset Interface Signals 9.2. Avalon® Memory-Mapped Interface Signals 9.3. Avalon® Streaming Interface Signals 9.4. PHY Interface Signals 9.5. Status Interface 9.6. IEEE 1588v2 Timestamp Interface Signals
10. Configuration Registers Description x
10.1. Register Access Definition 10.2. Low Latency Ethernet 10G MAC 10.3. PHY
10.3. PHY x
10.3.1. 1G/2.5G/5G/10G Multirate PHY
1. Quick Start Guide
2. 10M/100M/1G Ethernet Design Example
3. 1G Ethernet Design Example with IEEE 1588v2 Feature
4. 2.5G Ethernet Design Example
5. 2.5G Ethernet Design Example with IEEE 1588v2 Feature
6. 10G Ethernet Design Example
7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
8. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588 Design Example
9. Interface Signals Description
10. Configuration Registers Description
11. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
12. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

12. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

Document Version Quartus® Prime Version IP Version Changes
2024.10.07 24.3 3.0.0
  • Removed a note about Agilex™ 5 D-Series FPGAs and SoCs support in the Quick Start Guide topic.
  • Added aldec in the Directory Structure topic:
    • Updated Directory Structure for the Design Example.
    • Updated Directory and File Description table.
    • Updated Procedure topic for Simulating the Design.
  • Updated Example Design Tab figure.
  • Updated Signal Tap Debug Signals table to include tod_sampling_pll_locked signal description.
  • Added support for Riviera-PRO* simulator in all example designs.
  • Added information about the 10G design example:
    • Updated Directory Structure topic.
    • Updated Procedure topic for Simulating the Design.
    • Updated Reset Scheme for 10M/100M/1G Ethernet Design Example.
  • Changed 1G/2.5G Ethernet Design Example with IEEE 1588v2 to 1G Ethernet Design Example with IEEE 1588v2 and updated the following topics:
    • Changed all instances of 1G/2.5G to 1G.
    • Updated Features topic.
    • Updated Hardware and Software Requirements topic to add hardware requirements.
    • Updated figure title of Block Diagram—1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature to Block Diagram—1G Ethernet Design Example with IEEE 1588v2 Feature title.
    • Updated Interface Signals of the 1G Ethernet Design Examples with IEEE 1588v2 Feature figure.
    • Updated Clocking Scheme for 1G Ethernet Design Example with IEEE 1588v2 Feature diagram.
    • Added Hardware Testing topic.
  • Added a new topic about the 2.5G ethernet with IEEE 1588v2 feature design example variant.
  • Added a new topic about the 10G ethernet design example variant.
  • Added information about hardware testing for the 10M/100M/1G/2.5G/5G/10G (USXGMII) ethernet with IEEE 1588v2 feature design example variant:
    • Updated Hardware and Software Requirements.
    • Updated Design Components table.
    • Added Hardware Testing topic.
  • Updated Clocking Scheme for 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example With IEEE 1588v2 Feature figure.
  • Updated Reset Scheme for 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example With IEEE 1588v2 Feature figure.
  • Added in the Simulation topics in the following design examples:
    • 10M/100M/1G Ethernet Design Example
    • 2.5G Ethernet Design Example
    • 10G Ethernet Design Example
    • 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
  • Updated Interface Signal diagram for the 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588 Design Example.
  • Updated Clock and Reset Interface Signals to include mac_312_5_clk and refclk_p signals.
  • Updated 1G/2.5G/5G/10G Multirate PHY Register Definitions table to remove 0x461 word offset.
2024.07.08 24.2 2.1.0
  • Added a note about Agilex™ 5 D-Series FPGAs and SoCs support in the Quick Start Guide topic.
  • Updated Development Stages for the Design Example figure.
  • Updated Directory Structure for the Design Example diagram.
  • Updated synopsys/vcsmx to the Directory and File Description table.
  • Updated Example Design Tab figure.
  • Added a note in the Procedure topic in Generating the Design topic.
  • Updated the Parameters in the Example Design Tab table to include Generate Debug Signal Tap, Select Board, and Select Device Initialization Clock parameter.
  • Added VCS* MX simulation script and updated QuestaSim* command in the Procedure topic in Simulating the Design topic.
  • Updated Compiling and Configuring the Design Example in Hardware topic.
  • Added Signal Tap Debugging and Debugging Signals topics.
  • Updated the following topics for 10M/100M/1G ethernet design example:
    • Updated Hardware and Software Requirements topic to add VCS* MX support and add hardware testing requirements.
    • Updated Reset Scheme topic to add information about In-System Sources and Probes (ISSP).
    • Updated Reset Scheme for 10M/100M/1G Ethernet Design Example figure.
    • Added Hardware Testing topic.
    • Updated Interface Signals of the Design Example figure.
    • Updated Register Map table.
    • Added Packet Generator and Traffic Monitor Register Map topic.
  • Updated the following topics for 1G/2.5G ethernet design example:
    • Updated Hardware and Software Requirements topic to add VCS* MX support.
    • Updated Clocking Scheme for 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature figure.
    • Updated Interface Signals of the 1G/2.5G Ethernet Design Examples with IEEE 1588v2 Feature figure.
  • Updated the following topics for 2.5G ethernet design example:
    • Updated Hardware and Software Requirements topic to add VCS* MX support and add hardware testing requirements.
    • Updated Reset Scheme topic to add information about In-System Sources and Probes (ISSP).
    • Updated Reset Scheme for 2.5G Ethernet Design Example figure.
    • Added Hardware Testing topic.
    • Updated Interface Signals of the 2.5G Ethernet Design Example figure.
    • Updated Register Map table.
    • Added Packet Generator and Traffic Monitor Register Map topic.
  • Updated the following topics for 10M/100M/1G/2.5G/5G/10G (USXGMII) ethernet design example:
    • Updated Hardware and Software Requirements topic to add VCS* MX support and add hardware testing requirements.
    • Updated Reset Scheme topic to add information about In-System Sources and Probes (ISSP).
    • Added Hardware Testing topic.
    • Updated Interface Signals of the 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example figure.
    • Updated Register Map table.
    • Added Packet Generator and Traffic Monitor Register Map topic.
  • Added information about 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588 design example variant.
  • Updated the Avalon® Memory-Mapped Interface Signals table.
  • Updated 1G/2.5G/5G/10G Multirate PHY Register Definitions table to include datapath latency registers.
2024.04.01 24.1 2.0.0 Initial public release.
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