High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP User Guide

Download PDF
ID 773264
Date 12/04/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP User Guide 2. Introduction to High Bandwidth Memory 3. Intel Agilex® 7 M-Series HBM2E Architecture 4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP 5. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Interface 6. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Performance 7. Debugging the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP 8. Document Revision History for High Bandwidth Memory (HBM2E) Interface Intel FPGA IP User Guide A. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Intel® Quartus® Prime Software Flow
1. About the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP User Guide x
1.1. Release Information
2. Introduction to High Bandwidth Memory x
2.1. HBM2E in Intel Agilex® 7 M-Series Devices 2.2. HBM2E DRAM Structure 2.3. Intel Agilex® 7 HBM2E Features 2.4. Intel Agilex® 7 M-Series HBM2E Controller Features 2.5. Intel Agilex® 7 M-Series FPGA HBM2E IP Device Family Support
3. Intel Agilex® 7 M-Series HBM2E Architecture x
3.1. Intel Agilex® 7 M-Series HBM2E Introduction 3.2. Intel Agilex® 7 M-Series Hard Memory NoC Subsystem 3.3. Address Mapping of the HBM2E Targets 3.4. Intel Agilex® 7 M-Series UIB Architecture 3.5. Intel Agilex® 7 M-Series HBM2E Controller Architecture
3.5. Intel Agilex® 7 M-Series HBM2E Controller Architecture x
3.5.1. Intel Agilex® 7 M-Series HBM2E Controller Details HBM2E burst transactions User Interface vs HBM2E Interface Frequency Command Priority Starvation limit Command scheduling Address ordering Thermal Control Refresh requests Precharge policy Power down enable ECC HBM2E Controller features enabled by default
4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP x
4.1. Creating an Intel® Quartus® Prime Pro Edition Project for High Bandwidth Memory (HBM2E) Interface FPGA IP 4.2. Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP
4.2. Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP x
4.2.1. General Parameters for High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP 4.2.2. Example Design Parameters for High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP 4.2.3. Modifying Your Pin Assignments to Choose the Physical Location of the HBM2E Device
5. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Interface x
5.1. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP High Level Block Diagram 5.2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Controller Interface Signals 5.3. User AXI Interface Timing 5.4. Platform Designer-Only Interface 5.5. User Accesses to the HBM2E Controller
5.2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Controller Interface Signals x
5.2.1. Reset, Clock, and Calibration Status Signals 5.2.2. 'Do not connect' Signals 5.2.3. Asynchronous HBM2E Controller Signals 5.2.4. AXI4 Interface Signals 5.2.5. AXI4-Lite Interface
5.3. User AXI Interface Timing x
5.3.1. AXI Write Transaction 5.3.2. AXI Read Transaction
5.5. User Accesses to the HBM2E Controller x
5.5.1. Initialization Control Register and Initialization Status Register 5.5.2. Thermal Status Register 5.5.3. ECC Error Counters Register 5.5.4. Error Login Registers
6. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Performance x
6.1. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Controller Performance 6.2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP System Performance
6.1. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Controller Performance x
6.1.1. High Bandwidth Memory (HBM2E) DRAM Bandwidth 6.1.2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Efficiency 6.1.3. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Latency 6.1.4. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Timing
7. Debugging the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP x
7.1. Debugging Guidelines for High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP
A. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Intel® Quartus® Prime Software Flow x
A.1. Initiators Placement Recommendations A.2. Simulating HBM2E User Designs
1. About the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP User Guide
2. Introduction to High Bandwidth Memory
3. Intel Agilex® 7 M-Series HBM2E Architecture
4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP
5. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Interface
6. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Performance
7. Debugging the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP
8. Document Revision History for High Bandwidth Memory (HBM2E) Interface Intel FPGA IP User Guide
A. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Intel® Quartus® Prime Software Flow

3.5.1. Intel Agilex® 7 M-Series HBM2E Controller Details

This topic explains some of the high level HBM2E controller features.

HBM2E burst transactions

The HBM2E controller supports only the Pseudo Channel mode of accessing the HBM2E device; consequently, it can only support BL4 transactions to the DRAM. For improved efficiency, it supports the pseudo-BL8 mode, which performs two back-to-back BL4 transactions for each command queue entry.

Each BL4 transaction corresponds to 4*64 bits or 32 bytes and a pseudo-BL8 transaction corresponds to 64 bytes. You can select the burst transaction mode (32B or 64B) through the parameter editor.

User Interface vs HBM2E Interface Frequency

The user interface runs at a frequency lower than the HBM2E interface; the maximum interface frequency depends on the chosen device speed grade and the FPGA core logic frequency. The HBM2E interface frequency is independent of the core logic frequency.

Command Priority

You can set command priority for a write or read command request through the AXI interface: through the awqos signal in the AXI write address channel, or arqos in the AXI read address channel. The HBM2E controller supports normal and high priority levels. The controller executes commands with the same priority level in a round-robin scheme.

Starvation limit

The controller tracks how long each command waits and leaves no command unserviced in the command queue for a long period of time. The controller ensures that it serves every command efficiently.

Command scheduling

The HBM2E controller schedules the incoming commands to achieve maximum efficiency at the HBM2E interface. The HBM2E controller also follows the AXI ordering model of the AXI4 protocol specification.

Address ordering

The HBM2E controller supports different address ordering schemes that you can select for best efficiency given your use case. The chosen addressing scheme determines the order of address configurations in the AXI write and read address buses, including row address, column address, bank address, and stack ID (applicable only to the 8H devices). The HBM2E controller remaps the logical address of the command to a physical memory address.

Thermal Control

The HBM2E controller uses the TEMP and CATTRIP outputs from the HBM2E device to manage temperature variations inside the HBM2E stack.

  • Temperature compensated refresh (TEMP): The HBM2E DRAM provides temperature compensated refresh information to the controller through the TEMP[2:0] pins, which defines the proper refresh rate that the DRAM expects to maintain data integrity. The temp value is gray-coded and absolute temperature values for each encoding are vendor-specific. The encoding on the TEMP[2:0] pins reflects the required refresh rate for the hottest die in the stack. The TEMP data updates when the temperature exceeds vendor-specified threshold levels appropriate for each refresh rate.
    Table 5.  DRAM Refresh Timing
    TEMP [2:0] Refresh Rate
    000 4 x tREFI
    001 2 x tREFI
    011 1 x tREFI
    010 0.5 x tREFI
    110 0.25 x tREFI
    111 TBD
    101 TBD
    100 TBD
  • Catastrophic temperature sensor (CATTRIP): The CATTRIP sensor detects whether the junction temperature of any die in the stack exceeds the catastrophic trip threshold value CATTEMP. The device vendor programs the CATTEMP to a value less than the temperature at which permanent damage to the HBM stack would occur. The CATTEMP value is also the Absolute Max Junction temperature value as specified in the Intel Agilex® 7 M-Series data sheet for the family of devices that include the HBM2E DRAM.

    If a junction temperature anywhere in the stack exceeds the CATTEMP value, the HBM stack drives the external CATTRIP pin to 1, indicating that catastrophic damage may occur. When the CATTRIP pin is at 1, the controller stops all traffic to HBM and stalls indefinitely. To resolve the overheating situation and return the CATTRIP value to 0, remove power from the device and allow sufficient time for the device to cool before reapplying power.

  • Thermal throttling: Thermal throttling is a controller safety feature that helps control thermal runaway if the HBM2E die overheats, preventing a catastrophic failure. The desired throttling ratio, which determines the throttling frequency, can be specified for 2 temperature ranges: 85 to 94 degrees Celsius and 95 to 105 degrees Celsius. The throttling ratio for the 95 to 105 degree range should be greater than or equal to the ratio specified for the 85 to 94 degree range. No throttling is applied below 85 degrees and 100% throttling is applied above 105 degrees. The controller deasserts the AXI ready signals (awready, wready and arready) when it is actively throttling the input commands and data.

Refresh requests

The HBM2E controller handles HBM2E memory refresh requirements and issues refresh requests at the optimal time, as specified by the JEDEC specification of the HBM2E DRAM. The controller automatically controls refresh rates based on the temperature setting of the memory through the TEMP vector that the memory provides.

Precharge policy

The HBM2E controller issues precharge commands to the HBM2E memory based on the write/read transaction address. In addition, you can issue an auto-precharge request together with any AXI read or write command to the HBM2E controller.

There are two auto-precharge modes:

  • HINT – You can issue the auto-precharge request. The controller then decides whether to issue the precharge command, based on the contents of its command queues.
  • FORCED – You provide auto-precharge requests through the AXI interface and the precharge request executes.

Power down enable

To conserve power, the HBM2E controller can enter power-down mode when the bus is idle for a long time. You can select this option if required.

ECC

The HBM2E controller supports ECC. The ECC scheme implemented is single-bit error correction with double-bit error detection, with 64-bits of data and 8-bits of ECC code (also known as the syndrome).

HBM2E Controller features enabled by default

The HBM2E controller enables the following features by default:

  • DBI – The DBI option supports both write and read DBI, and optimizes signal integrity/power consumption by restricting signal switching on the HBM2E DQ bus.
  • Parity – Supports command/address parity and DQ parity.
Level Two Title