High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP User Guide

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Date 12/04/2023
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Document Table of Contents
Document Table of Contents x
1. About the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP User Guide 2. Introduction to High Bandwidth Memory 3. Intel Agilex® 7 M-Series HBM2E Architecture 4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP 5. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Interface 6. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Performance 7. Debugging the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP 8. Document Revision History for High Bandwidth Memory (HBM2E) Interface Intel FPGA IP User Guide A. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Intel® Quartus® Prime Software Flow
1. About the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP User Guide x
1.1. Release Information
2. Introduction to High Bandwidth Memory x
2.1. HBM2E in Intel Agilex® 7 M-Series Devices 2.2. HBM2E DRAM Structure 2.3. Intel Agilex® 7 HBM2E Features 2.4. Intel Agilex® 7 M-Series HBM2E Controller Features 2.5. Intel Agilex® 7 M-Series FPGA HBM2E IP Device Family Support
3. Intel Agilex® 7 M-Series HBM2E Architecture x
3.1. Intel Agilex® 7 M-Series HBM2E Introduction 3.2. Intel Agilex® 7 M-Series Hard Memory NoC Subsystem 3.3. Address Mapping of the HBM2E Targets 3.4. Intel Agilex® 7 M-Series UIB Architecture 3.5. Intel Agilex® 7 M-Series HBM2E Controller Architecture
3.5. Intel Agilex® 7 M-Series HBM2E Controller Architecture x
3.5.1. Intel Agilex® 7 M-Series HBM2E Controller Details
4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP x
4.1. Creating an Intel® Quartus® Prime Pro Edition Project for High Bandwidth Memory (HBM2E) Interface FPGA IP 4.2. Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP
4.2. Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP x
4.2.1. General Parameters for High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP 4.2.2. Example Design Parameters for High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP 4.2.3. Modifying Your Pin Assignments to Choose the Physical Location of the HBM2E Device
5. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Interface x
5.1. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP High Level Block Diagram 5.2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Controller Interface Signals 5.3. User AXI Interface Timing 5.4. Platform Designer-Only Interface 5.5. User Accesses to the HBM2E Controller
5.2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Controller Interface Signals x
5.2.1. Reset, Clock, and Calibration Status Signals 5.2.2. 'Do not connect' Signals 5.2.3. Asynchronous HBM2E Controller Signals 5.2.4. AXI4 Interface Signals 5.2.5. AXI4-Lite Interface
5.3. User AXI Interface Timing x
5.3.1. AXI Write Transaction 5.3.2. AXI Read Transaction
5.5. User Accesses to the HBM2E Controller x
5.5.1. Initialization Control Register and Initialization Status Register 5.5.2. Thermal Status Register 5.5.3. ECC Error Counters Register 5.5.4. Error Login Registers
6. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Performance x
6.1. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Controller Performance 6.2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP System Performance
6.1. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Controller Performance x
6.1.1. High Bandwidth Memory (HBM2E) DRAM Bandwidth 6.1.2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Efficiency 6.1.3. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Latency 6.1.4. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Timing
7. Debugging the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP x
7.1. Debugging Guidelines for High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP
A. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Intel® Quartus® Prime Software Flow x
A.1. Initiators Placement Recommendations A.2. Simulating HBM2E User Designs
1. About the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP User Guide
2. Introduction to High Bandwidth Memory
3. Intel Agilex® 7 M-Series HBM2E Architecture
4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP
5. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Interface
6. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Performance
7. Debugging the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP
8. Document Revision History for High Bandwidth Memory (HBM2E) Interface Intel FPGA IP User Guide
A. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Intel® Quartus® Prime Software Flow

5.2.5. AXI4-Lite Interface

The AXI4-Lite interface allows access to the high-bandwidth memory controller's control and status registers. The AXI4-Lite interface is intended primarily for use in relatively low bandwidth sideband operations.
Table 28.  Write Address (Command) Channel
Port Name Width Direction Description
sb_awaddr 27 Input Write Address. Target address of the AXI4-Lite write command.
sb_awvalid 1 Input Write Address Valid. This signal indicates that valid write address information is available.
sb_awready 1 Output Write Address Channel Ready. This signal indicates that the slave is ready to accept a write command.
sb_awprot 3 Input

Protection Type. [Reserved for Future Use]. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access.

Table 29.  Write Data Channel
Port Name Width Direction Description
sb_wdata 32 Input Write Data.
sb_wstrb 4 Input Write Strobes (Byte Enables). This signal indicates which byte lanes (for sb_wdata) hold valid data. There is one write strobe bit for each eight bits of the write data bus.
sb_wvalid 1 Input Write Valid. This signal indicates that valid write data and strobes are available.
sb_wready 1 Output Write Ready. This signal indicates that the slave (HBM controller) can accept the write data.
Table 30.  Write Response Channel
Port Name Width Direction Description
sb_bresp 2 Output Write Response. This signal indicates the result of the most recent write command.
Value Meaning
2’b00 OKAY
2’b10 SLVERR
sb_bvalid 1 Output Write Response Valid. This signal indicates that a valid write response is available.
sb_bready 1 Input Response Ready. This signal indicates that the master can accept a write response.
Table 31.  Read Address (Command) Channel
Port Name Width Direction Description
sb_araddr 27 Input Read Address. Target address of the AXI4-Lite read command.
sb_arvalid 1 Input Read Address Valid. This signal indicates that a valid read address is available.
sb_arready 1 Output Read Address Ready. This signal indicates that the slave is ready to accept a read command.
sb_arprot 3 Input

Protection Type. [Reserved for Future Use]. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access.

Table 32.  Read Data Channel
Port Name Width Direction Description
sb_rdata 32 Output Read Data.
sb_rresp 2 Output Read Response. This signal indicates the result of the most recent read command.
Value Meaning
2’b00 OKAY
2’b10 SLVERR
sb_rvalid 1 Output Read Valid. This signal indicates that a valid read response is available.
sb_rready 1 Input Read Ready. This signal indicates that the master can accept the read data and response information.
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