High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP User Guide

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ID 773264
Date 12/04/2023
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Document Table of Contents
Document Table of Contents x
1. About the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP User Guide 2. Introduction to High Bandwidth Memory 3. Intel Agilex® 7 M-Series HBM2E Architecture 4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP 5. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Interface 6. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Performance 7. Debugging the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP 8. Document Revision History for High Bandwidth Memory (HBM2E) Interface Intel FPGA IP User Guide A. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Intel® Quartus® Prime Software Flow
1. About the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP User Guide x
1.1. Release Information
2. Introduction to High Bandwidth Memory x
2.1. HBM2E in Intel Agilex® 7 M-Series Devices 2.2. HBM2E DRAM Structure 2.3. Intel Agilex® 7 HBM2E Features 2.4. Intel Agilex® 7 M-Series HBM2E Controller Features 2.5. Intel Agilex® 7 M-Series FPGA HBM2E IP Device Family Support
3. Intel Agilex® 7 M-Series HBM2E Architecture x
3.1. Intel Agilex® 7 M-Series HBM2E Introduction 3.2. Intel Agilex® 7 M-Series Hard Memory NoC Subsystem 3.3. Address Mapping of the HBM2E Targets 3.4. Intel Agilex® 7 M-Series UIB Architecture 3.5. Intel Agilex® 7 M-Series HBM2E Controller Architecture
3.5. Intel Agilex® 7 M-Series HBM2E Controller Architecture x
3.5.1. Intel Agilex® 7 M-Series HBM2E Controller Details
4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP x
4.1. Creating an Intel® Quartus® Prime Pro Edition Project for High Bandwidth Memory (HBM2E) Interface FPGA IP 4.2. Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP
4.2. Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP x
4.2.1. General Parameters for High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP 4.2.2. Example Design Parameters for High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP 4.2.3. Modifying Your Pin Assignments to Choose the Physical Location of the HBM2E Device
5. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Interface x
5.1. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP High Level Block Diagram 5.2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Controller Interface Signals 5.3. User AXI Interface Timing 5.4. Platform Designer-Only Interface 5.5. User Accesses to the HBM2E Controller
5.2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Controller Interface Signals x
5.2.1. Reset, Clock, and Calibration Status Signals 5.2.2. 'Do not connect' Signals 5.2.3. Asynchronous HBM2E Controller Signals 5.2.4. AXI4 Interface Signals 5.2.5. AXI4-Lite Interface
5.3. User AXI Interface Timing x
5.3.1. AXI Write Transaction 5.3.2. AXI Read Transaction
5.5. User Accesses to the HBM2E Controller x
5.5.1. Initialization Control Register and Initialization Status Register 5.5.2. Thermal Status Register 5.5.3. ECC Error Counters Register 5.5.4. Error Login Registers
6. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Performance x
6.1. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Controller Performance 6.2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP System Performance
6.1. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Controller Performance x
6.1.1. High Bandwidth Memory (HBM2E) DRAM Bandwidth 6.1.2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Efficiency 6.1.3. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Latency 6.1.4. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Timing
7. Debugging the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP x
7.1. Debugging Guidelines for High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP
A. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Intel® Quartus® Prime Software Flow x
A.1. Initiators Placement Recommendations A.2. Simulating HBM2E User Designs
1. About the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP User Guide
2. Introduction to High Bandwidth Memory
3. Intel Agilex® 7 M-Series HBM2E Architecture
4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP
5. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Interface
6. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Performance
7. Debugging the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP
8. Document Revision History for High Bandwidth Memory (HBM2E) Interface Intel FPGA IP User Guide
A. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Intel® Quartus® Prime Software Flow

6.1.1. High Bandwidth Memory (HBM2E) DRAM Bandwidth

For each HBM2E DRAM in an Intel Agilex® 7 device, there are eight channels of 128-bits each. The following example illustrates the calculation of bandwidth offered by one HBM2E interface.

Assuming an interface running at 1.6 GHz: 128 DQ × 1.6 GHz = 204.8 Gbps

  • The interface operates in double data-rate mode, so the total bandwidth per HBM2E is: 204.8 Gbps × 2 = 409.6 Gbps.
  • The total bandwidth for the HBM2E interface is: 409.6 Gbps × 8 channels = 409.6 GByte/sec.
  • If the HBM2E controller operates at 90% efficiency, the effective bandwidth is: 409.6 GByte/sec × 0.9 = ~368 GByte/sec.
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