High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP User Guide

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ID 773264
Date 12/04/2023
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Document Table of Contents
Document Table of Contents x
1. About the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP User Guide 2. Introduction to High Bandwidth Memory 3. Intel Agilex® 7 M-Series HBM2E Architecture 4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP 5. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Interface 6. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Performance 7. Debugging the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP 8. Document Revision History for High Bandwidth Memory (HBM2E) Interface Intel FPGA IP User Guide A. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Intel® Quartus® Prime Software Flow
1. About the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP User Guide x
1.1. Release Information
2. Introduction to High Bandwidth Memory x
2.1. HBM2E in Intel Agilex® 7 M-Series Devices 2.2. HBM2E DRAM Structure 2.3. Intel Agilex® 7 HBM2E Features 2.4. Intel Agilex® 7 M-Series HBM2E Controller Features 2.5. Intel Agilex® 7 M-Series FPGA HBM2E IP Device Family Support
3. Intel Agilex® 7 M-Series HBM2E Architecture x
3.1. Intel Agilex® 7 M-Series HBM2E Introduction 3.2. Intel Agilex® 7 M-Series Hard Memory NoC Subsystem 3.3. Address Mapping of the HBM2E Targets 3.4. Intel Agilex® 7 M-Series UIB Architecture 3.5. Intel Agilex® 7 M-Series HBM2E Controller Architecture
3.5. Intel Agilex® 7 M-Series HBM2E Controller Architecture x
3.5.1. Intel Agilex® 7 M-Series HBM2E Controller Details
4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP x
4.1. Creating an Intel® Quartus® Prime Pro Edition Project for High Bandwidth Memory (HBM2E) Interface FPGA IP 4.2. Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP
4.2. Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP x
4.2.1. General Parameters for High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP 4.2.2. Example Design Parameters for High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP 4.2.3. Modifying Your Pin Assignments to Choose the Physical Location of the HBM2E Device
5. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Interface x
5.1. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP High Level Block Diagram 5.2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Controller Interface Signals 5.3. User AXI Interface Timing 5.4. Platform Designer-Only Interface 5.5. User Accesses to the HBM2E Controller
5.2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Controller Interface Signals x
5.2.1. Reset, Clock, and Calibration Status Signals 5.2.2. 'Do not connect' Signals 5.2.3. Asynchronous HBM2E Controller Signals 5.2.4. AXI4 Interface Signals 5.2.5. AXI4-Lite Interface
5.3. User AXI Interface Timing x
5.3.1. AXI Write Transaction 5.3.2. AXI Read Transaction
5.5. User Accesses to the HBM2E Controller x
5.5.1. Initialization Control Register and Initialization Status Register 5.5.2. Thermal Status Register 5.5.3. ECC Error Counters Register 5.5.4. Error Login Registers
6. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Performance x
6.1. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Controller Performance 6.2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP System Performance
6.1. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Controller Performance x
6.1.1. High Bandwidth Memory (HBM2E) DRAM Bandwidth 6.1.2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Efficiency 6.1.3. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Latency 6.1.4. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Timing
7. Debugging the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP x
7.1. Debugging Guidelines for High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP
A. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Intel® Quartus® Prime Software Flow x
A.1. Initiators Placement Recommendations A.2. Simulating HBM2E User Designs
1. About the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP User Guide
2. Introduction to High Bandwidth Memory
3. Intel Agilex® 7 M-Series HBM2E Architecture
4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP
5. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Interface
6. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Performance
7. Debugging the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP
8. Document Revision History for High Bandwidth Memory (HBM2E) Interface Intel FPGA IP User Guide
A. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Intel® Quartus® Prime Software Flow

3.2. Intel Agilex® 7 M-Series Hard Memory NoC Subsystem

The Intel Agilex® 7 M-series FPGAs are integrated with a hard memory network-on-chip (NoC), which is a hardened block primarily intended to facilitate high-bandwidth data movement from the FPGA core fabric to periphery and vice-versa.
Note: As a prerequisite to this content, please review the first three chapters of the Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide .

The hard memory NoC is implemented as two high-speed interconnect NoC subsystems which run horizontally along the top and bottom edges of the die.

Each high-speed interconnect NoC subsystem consists of a PLL, a subsystem manager (SSM), and multiple NoC segments that contain the following:

  • Initiator – Initiator NoC Interface Unit . An AXI bridge onto the NoC. An initiator is an AXI slave that converts AXI commands from a design in the FPGA fabric into NoC requests and converts NoC responses back into AXI responses to the user's design.
  • Target – Target NoC Interface Unit . A bridge from the NoC to an AXI target in the periphery of the FPGA device. This is a NoC target and acts as an AXI master to the peripheral, such as a memory controller.
  • Switch – act as routers for the requests.

M-series FPGAs include two separate high-speed interconnect NoC subsystems, identified as top and bottom. The top and bottom NoC subsystem interfaces with UIB, IO96B, HPS and core fabric. With the fabric NoC option, the AXI read response data is routed into the fabric via M20K columns instead of being delivered to initiators read data port. This reduces fabric routing utilization and improves read response data throughput.

NoC Subsystem for HBM2E Read-Write Operations

In Intel Agilex® 7 M-series FPGAs, fabric access to the HBM2E DRAM memory is exclusively via the hard memory NoC. Direct fabric access to and from the HBM2E DRAM is not supported, as illustrated in Figure 1.

The HBM2E DRAM memory connects to the UIB through the EMIB. The UIB interfaces with user logic via the integrated hardened memory NoC using the AXI4 protocol. The hard memory NoC enables a single AXI master in the user logic to access data in multiple pseudo-channels.

Figure 3. Abstract Block Diagram of HBM2E IP Components
Note: The above figure is an abstract diagram and is not intended to accurately represent the physical layout of the related blocks.

As illustrated in Figure 1, the read and write transactions are routed from the FPGA’s user logic to the initiators through their AXI interfaces. The initiators face the fabric and are part of the hard memory NoC block. Initiators convert the AXI-based transactions to the packet-based protocol used by the hard memory NoC. The transactions are routed to their appropriate targets, through the hard memory NoC. The targets convert the packet-based traffic back to AXI. The targets face the UIB and connect to each of the controller's pseudo-channels. From the HBM controller channel the transactions are transferred to the HBM2E DRAM through the PHY and I/Os.

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