High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP User Guide

ID 773264
Date 12/04/2023
Public

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2.2. HBM2E DRAM Structure

The HBM2E DRAM is optimized for high-bandwidth operation using a stack of multiple DRAM devices exposing several independent interfaces called channels. Each DRAM stack supports eight channels.

The following figure shows an example stack containing four DRAM dies, each die supporting two channels. Each die contributes additional capacity and additional channels to the stack, up to a maximum of eight channels per stack. Each channel provides access to an independent set of DRAM banks. Requests from one channel may not access data attached to a different channel.

Figure 2. High Bandwidth Memory Stack Consisting of Four DRAM Dies