High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP User Guide

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Date 12/04/2023
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Document Table of Contents
Document Table of Contents x
1. About the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP User Guide 2. Introduction to High Bandwidth Memory 3. Intel Agilex® 7 M-Series HBM2E Architecture 4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP 5. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Interface 6. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Performance 7. Debugging the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP 8. Document Revision History for High Bandwidth Memory (HBM2E) Interface Intel FPGA IP User Guide A. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Intel® Quartus® Prime Software Flow
1. About the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP User Guide x
1.1. Release Information
2. Introduction to High Bandwidth Memory x
2.1. HBM2E in Intel Agilex® 7 M-Series Devices 2.2. HBM2E DRAM Structure 2.3. Intel Agilex® 7 HBM2E Features 2.4. Intel Agilex® 7 M-Series HBM2E Controller Features 2.5. Intel Agilex® 7 M-Series FPGA HBM2E IP Device Family Support
3. Intel Agilex® 7 M-Series HBM2E Architecture x
3.1. Intel Agilex® 7 M-Series HBM2E Introduction 3.2. Intel Agilex® 7 M-Series Hard Memory NoC Subsystem 3.3. Address Mapping of the HBM2E Targets 3.4. Intel Agilex® 7 M-Series UIB Architecture 3.5. Intel Agilex® 7 M-Series HBM2E Controller Architecture
3.5. Intel Agilex® 7 M-Series HBM2E Controller Architecture x
3.5.1. Intel Agilex® 7 M-Series HBM2E Controller Details
4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP x
4.1. Creating an Intel® Quartus® Prime Pro Edition Project for High Bandwidth Memory (HBM2E) Interface FPGA IP 4.2. Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP
4.2. Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP x
4.2.1. General Parameters for High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP 4.2.2. Example Design Parameters for High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP 4.2.3. Modifying Your Pin Assignments to Choose the Physical Location of the HBM2E Device
5. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Interface x
5.1. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP High Level Block Diagram 5.2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Controller Interface Signals 5.3. User AXI Interface Timing 5.4. Platform Designer-Only Interface 5.5. User Accesses to the HBM2E Controller
5.2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Controller Interface Signals x
5.2.1. Reset, Clock, and Calibration Status Signals 5.2.2. 'Do not connect' Signals 5.2.3. Asynchronous HBM2E Controller Signals 5.2.4. AXI4 Interface Signals 5.2.5. AXI4-Lite Interface
5.3. User AXI Interface Timing x
5.3.1. AXI Write Transaction 5.3.2. AXI Read Transaction
5.5. User Accesses to the HBM2E Controller x
5.5.1. Initialization Control Register and Initialization Status Register 5.5.2. Thermal Status Register 5.5.3. ECC Error Counters Register 5.5.4. Error Login Registers
6. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Performance x
6.1. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Controller Performance 6.2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP System Performance
6.1. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Controller Performance x
6.1.1. High Bandwidth Memory (HBM2E) DRAM Bandwidth 6.1.2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Efficiency 6.1.3. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Latency 6.1.4. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Timing
7. Debugging the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP x
7.1. Debugging Guidelines for High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP
A. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Intel® Quartus® Prime Software Flow x
A.1. Initiators Placement Recommendations A.2. Simulating HBM2E User Designs
1. About the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP User Guide
2. Introduction to High Bandwidth Memory
3. Intel Agilex® 7 M-Series HBM2E Architecture
4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP
5. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Interface
6. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Performance
7. Debugging the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP
8. Document Revision History for High Bandwidth Memory (HBM2E) Interface Intel FPGA IP User Guide
A. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Intel® Quartus® Prime Software Flow

4.2.2. Example Design Parameters for High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP

The Example Design tab allows you to configure example design files for simulation and synthesis.
Figure 13. Example Design tab of HBM2E IP Parameters
Table 11.  Group: Example Design / Example Design NoC Clocks and Connectivity
Display Name Description
Reference clock frequency for example design NoC Clock Control IP When running the design example on hardware, you can override this setting to match the NoC reference clock generated by your board.
Choose initiator to target NoC mapping

You can choose between two configurations of initiator to target hard memory NoC mapping for the design example:

  • 1 to 1 full address connection: each traffic generator in the example design uses its NOC initiator to access the full address range of the NOC target connected to a single HBM pseudo-channel. Each initiator dedicatedly connects to single target.
  • 16 to 16 cross bar: Each of the 16 traffic generators drives traffic to all of the 16 pseudo-channels. This option is only available when all 8 controller channels are enabled.
Use Fabric NoC to return read responses via M20Ks

When you enable any option other than Fabric NoC will not be used by the example design, the NoC initiator IP uses the fabric's M20K-based memories to deliver AXI read responses deep into the fabric. 512-bits of read response data are returned to your design in each AXI interface, enabling fabric frequencies above 350 MHz to saturate HBM2E pseudo-channel read bandwidth.

You can enable the Fabric NoC for one of the following configurations:

512-bit wide data paths. 256-bit NoC bridge hardware has an independent clock: Configures the NoC Initiator IP with a single 512-bit wide AXI interface for both read and write data paths, in which case the NoC bridge hardware must be supplied with its own clock.

The following two configurations are asymmetric modes in which the NoC Initiator IP has separate 512-bit wide read and 256-bit wide write data paths. These paths can have a common clock , but giving the wide read data paths their own clock enables a higher frequency to be used for the write interface:

  • 256-bit write and 512-bit read data paths, with a common clock.
  • 256-bit write and 512-bit read data paths, read data paths has it own clock.
AXI4-Lite support

Select this option to choose a design example that includes AXI4-Lite interfaces in the fabric. The AXI4-Lite interface provides access to control and status registers. You must enable this option if you want to access the control and status registers of the HBM2E IP.

  • Select None if you don't want to enable AXI4-Lite in your design.
  • Select Dedicated AXI4-Lite NoC Initiator to enable AXI4-Lite access. This option adds one more instance of the NoC initiator IP with a seventeenth initiator which is used to send out AXI4-Lite traffic.
  • Select Shared NoC Initiator for AXI4 and AXI4-Lite to share the initiator with AXI4 main-band and AXI4-Lite traffic. You cannot use this option when there are HBM2E channels that have been configured in a 288-bit data mode. AXI4-Lite support via a shared initiator cannot be combined with use of the fabric NoC.
Note: You cannot enable an AXI4-Lite interface with 288-bit data mode designs.

Refer to the Use Cases topic in the HBM2E IP Design Example User Guide for more detailed information on the implementation of these options.

NoC read bandwidth The anticipated read bandwidth requirement, in GBps, for each NoC initiator bridge-to-target bridge (I-T) connection. The Intel® Quartus® PrimeCompiler uses this information to analyze whether there is congestion on the hard memory NoC. This is a default value selected based on the most optimal configuration and initiator placements. This assignment is made consistently to all I-T connections in the design. The performance analysis tool may flag warnings if these requirements lead to potential congestion on the NoC. Such a design can still be fully compiled and run on hardware but may cause sub-optimal performance. These settings can be changed independently for each I-T connection in the design in the NoC assignment editor.
NoC write bandwidth The anticipated write bandwidth requirement, in GBps, for each NoC initiator bridge-to-target bridge (I-T) connection. The Intel® Quartus® Prime Compiler uses this information to analyze whether there is congestion on the hard memory NoC. This is a default value selected based on the most optimal configuration and initiator placements. This assignment is made consistently to all I-T connections in the design. The performance analysis tool may flag warnings if these requirements lead to potential congestion on the NoC. Such a design can still be fully compiled and run on hardware but may cause sub-optimal performance. These settings can be changed independently for each I-T connection in the design in the NoC assignment editor.
NoC read transaction size The anticipated read transaction length requirement, in B, for each NoC initiator bridge-to-target bridge (I-T) connection. The Intel® Quartus® Prime Compiler uses this information to analyze whether there is congestion on the hard memory NoC. This is a default value selected based on the most optimal configuration and initiator placements. This assignment is made consistently to all I-T connections in the design. The performance analysis tool may flag warnings if these requirements lead to potential congestion on the NoC. Such a design can still be fully compiled and run on hardware but may cause sub-optimal performance. These settings can be changed independently for each I-T connection in the design in the NoC assignment editor.
NoC write transaction size The anticipated write transaction length requirement, in B, for each NoC initiator bridge-to-target bridge (I-T) connection. The Intel® Quartus® Prime Compiler uses this information to analyze whether there is congestion on the hard memory NoC. This is a default value selected based on the most optimal configuration and initiator placements. This assignment is made consistently to all I-T connections in the design. The performance analysis tool may flag warnings if these requirements lead to potential congestion on the NoC. Such a design can still be fully compiled and run on hardware but may cause sub-optimal performance. These settings can be changed independently for each I-T connection in the design in the NoC assignment editor.

Table 12.  Group: Example Designs / Example Design Clocks
Display Name Description
Core clock frequency The frequency of the core clock used to drive the design example's traffic generators and the NoC initiator IP interfaces to which they connect. In cases of fabric NoC designs with 512-bit wide data paths, the NoC initiator IP have their own clock.

Valid range of core clock frequencies depends on device speed grade and design details. Maximum values apply to all designs, while recommended values are based on the design example without fabric NoC.

Device Speed Grade Max Core Clock Recommended Core Clock
-3 450 MHz 430 MHz
-2 630 MHz 500 MHz
-1 660 MHz 545 MHz

For designs using fabric NoC, refer to the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP Design Example User Guide.

NoC bridge hardware frequency Specifies the frequency of the clock that the design example uses to drive the 256-bit wide NoC bridge hardware when you configure the design example to generate NoC Initiator IP with 512-bit data paths.

The following table shows the maximum operating frequency of the NoC bridge hardware for a design using Fabric NoC:

Device Speed Grade Max Operating NoC Bridge Clock
-3 450 MHz
-2 630 MHz
-1 660 MHz

For information on different fabric NoC configurations, refer to the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP Design Example User Guide.

Note: This parameter is available only when you choose a fabric NoC configuration of 512-bit wide data paths. 256-bit NoC bridge hardware has an independent clock.
Reference clock frequency for example design core clock PLL Reference clock frequency for the PLL supplying the core clock. This parameter affects only the design example PLL.
Read-only AXI data path frequency Specifies the clock frequency of the NoC initiator IP read interface when you configure the design example to generate NoC Initiator IP with separately clocked asymmetric-width read and write interfaces.

The following table shows the minimum operating frequency to drive the 512-bit read-only AXI data path frequency:

Device Speed Grade Min Operating Read-Only AXI Data Path Freq.
-3 350 MHz
-2 350 MHz
-1 250 MHz
Note: This parameter is available only when you choose a fabric NoC configuration of 256-bit wide and 512-bit read data paths, read data path has its own clock.
Table 13.  Group: Example Designs / Traffic Generator
Display Name Description
Select default traffic pattern This option allows you to select the traffic pattern type and how many read and write transactions to run in the design example simulation.
Table 14.  Group: Example Designs / Performance Monitor
Display Name Description
Enable performance monitoring Select this option to enable the performance monitor on all active HBM2E channels for measuring read and write transaction metrics.
Table 15.  Group: Example Designs / Example Design Files
Display Name Description
Simulation

Specifies that the system generate all necessary file sets for simulation when you click Generate Example Design.

If you do not enable this parameter, the system does not generate simulation file sets. Instead, the output directory contains the ed_sim.qsys file which contains details of the simulation example design for Platform Designer, and a make_sim_design.tcl file with other corresponding tcl files.

You can run the make_sim_design.tcl file from a command line to generate a simulation example design. The generated example designs for various simulators reside in the /sim subdirectory.

Synthesis

Specifies that the system generate all necessary file sets for synthesis when you click Generate Example Design.

If you do not enable this parameter, the system does not generate synthesis file sets. Instead, the output directory contains the ed_synth.qsys file which contains details of the synthesis example design for Platform Designer, and a make_qii_design.tcl file with other corresponding tcl files.

You can run the make_qii_design.tcl file from a command line to generate a synthesis example design. The generated example design resides in the /qii subdirectory.

Table 16.  Group: Example Designs / Generated HDL Format
Display Name Description
Simulation HDL format Format of HDL files generated for simulating the design example.
Level Two Title