High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP User Guide

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Date 12/04/2023
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Document Table of Contents
Document Table of Contents x
1. About the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP User Guide 2. Introduction to High Bandwidth Memory 3. Intel Agilex® 7 M-Series HBM2E Architecture 4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP 5. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Interface 6. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Performance 7. Debugging the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP 8. Document Revision History for High Bandwidth Memory (HBM2E) Interface Intel FPGA IP User Guide A. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Intel® Quartus® Prime Software Flow
1. About the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP User Guide x
1.1. Release Information
2. Introduction to High Bandwidth Memory x
2.1. HBM2E in Intel Agilex® 7 M-Series Devices 2.2. HBM2E DRAM Structure 2.3. Intel Agilex® 7 HBM2E Features 2.4. Intel Agilex® 7 M-Series HBM2E Controller Features 2.5. Intel Agilex® 7 M-Series FPGA HBM2E IP Device Family Support
3. Intel Agilex® 7 M-Series HBM2E Architecture x
3.1. Intel Agilex® 7 M-Series HBM2E Introduction 3.2. Intel Agilex® 7 M-Series Hard Memory NoC Subsystem 3.3. Address Mapping of the HBM2E Targets 3.4. Intel Agilex® 7 M-Series UIB Architecture 3.5. Intel Agilex® 7 M-Series HBM2E Controller Architecture
3.5. Intel Agilex® 7 M-Series HBM2E Controller Architecture x
3.5.1. Intel Agilex® 7 M-Series HBM2E Controller Details
4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP x
4.1. Creating an Intel® Quartus® Prime Pro Edition Project for High Bandwidth Memory (HBM2E) Interface FPGA IP 4.2. Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP
4.2. Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP x
4.2.1. General Parameters for High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP 4.2.2. Example Design Parameters for High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP 4.2.3. Modifying Your Pin Assignments to Choose the Physical Location of the HBM2E Device
5. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Interface x
5.1. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP High Level Block Diagram 5.2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Controller Interface Signals 5.3. User AXI Interface Timing 5.4. Platform Designer-Only Interface 5.5. User Accesses to the HBM2E Controller
5.2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Controller Interface Signals x
5.2.1. Reset, Clock, and Calibration Status Signals 5.2.2. 'Do not connect' Signals 5.2.3. Asynchronous HBM2E Controller Signals 5.2.4. AXI4 Interface Signals 5.2.5. AXI4-Lite Interface
5.3. User AXI Interface Timing x
5.3.1. AXI Write Transaction 5.3.2. AXI Read Transaction
5.5. User Accesses to the HBM2E Controller x
5.5.1. Initialization Control Register and Initialization Status Register 5.5.2. Thermal Status Register 5.5.3. ECC Error Counters Register 5.5.4. Error Login Registers
6. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Performance x
6.1. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Controller Performance 6.2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP System Performance
6.1. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Controller Performance x
6.1.1. High Bandwidth Memory (HBM2E) DRAM Bandwidth 6.1.2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Efficiency 6.1.3. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Latency 6.1.4. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Timing
7. Debugging the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP x
7.1. Debugging Guidelines for High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP
A. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Intel® Quartus® Prime Software Flow x
A.1. Initiators Placement Recommendations A.2. Simulating HBM2E User Designs
1. About the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP User Guide
2. Introduction to High Bandwidth Memory
3. Intel Agilex® 7 M-Series HBM2E Architecture
4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP
5. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Interface
6. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Performance
7. Debugging the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP
8. Document Revision History for High Bandwidth Memory (HBM2E) Interface Intel FPGA IP User Guide
A. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Intel® Quartus® Prime Software Flow

4.2.1. General Parameters for High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP

The General tab allows you to select HBM2E device configurations, the number of channels that you want to implement, and the controller settings.
Figure 8. Group: General / Quick Settings
Table 6.  Group: General / Quick Settings
Display Name Description
Speed Grade

Speed grade of FPGA device and whether it is an engineering sample (ES) or a production device. The value is automatically determined based on the device selected under View > Device Family. If you do not specify a device, the system assumes a production device of the fastest speed grade. You should always specify the correct target device during IP generation; failure to specify the correct device may result in generated IP that does not work on hardware.

HBM Device Type

The HBM device type. HBM_DEVICE_16GB_8HI refers to HBM2E device with a total device density of 16GB in a 8-high stack. HBM_DEVICE_8GB_4HI refers to an HBM2E device with a total density of 8GB in a 4-high stack.

Memory clock frequency

The frequency of the memory clock in MHz. Specifies the clock frequency for the HBM2E interface. The minimum supported memory clock frequency is 800 MHz and the maximum supported memory clock frequency depends on the FPGA device speed grade.

  • 1 speed grade: 1600 MHz
  • 2 speed grade: 1400 MHz
  • 3 speed grade: 1000 MHz
PLL reference clock frequency When checked the default value of 100 MHz is used for the PLL reference clock frequency. Uncheck the check box if you want to specify your own PLL reference clock frequency.
Memory PLL reference clock I/O standard Specifies the I/O standard for the PLL reference clock of the memory interface. The only supported termination option is LVDS with on-chip termination.
Channel enables Select number of channels you want to enable for your HBM2E IP. Each channel selection activates the controllers for the two pseudo-channels of that channel of the UIB block.
Figure 9. Group: General / Controller Configuration
Table 7.  Group: General / Controller Configuration
Display Name Description
Is clone of

Set this option to make this channel configuration a clone of the selected channel. Parameters are copied from the specified channel. This parameter applies when you enable more than one HBM2E channel.

Address Re-ordering Specifies the pattern for mapping the address from the AXI interface to the HBM2E memory device. By choosing an appropriate address reordering configuration, you help to improve the efficiency of accesses to the HBM2E memory device for the traffic pattern generated by your design. The HBM controller supports three types of address reordering:
  • SID-BG-BANK-ROW-COL
  • SID-ROW-BANK-COL-BG
  • ROW-SID-BANK-COL-BG
Note: The SID-BG-BANK-ROW-COL[5:1] address order limits HBM throughput when memory accesses are sequential, and also affects random access throughput in pseudo-BL8 mode.
Enable Auto-Precharge Control Select this parameter to enable the auto-precharge control on the controller top level. If you assert the auto-precharge control signal while requesting a read or write burst, you can specify whether the controller should close (precharge) the currently open page at the end of the read or write burst, potentially making a future access to a different page of the same bank faster.
User Read Auto-Precharge Policy Controls the amount of freedom that the controller has when handling auto-precharge requests. FORCED indicates that the controller follows the user auto-precharge request exactly. HINT indicates that the controller may override the auto-precharge request by disabling it when a page hit is detected (that is, if it receives two commands, one with auto-precharge and one without auto-precharge to the same page, the controller changes auto-precharge for the first to 0 so that the second can access the page without reopening it). You can issue the request to precharge together with the read command by asserting aruser[0]. You can choose between two values for this parameter:
  • RDAP_FORCED mode, in which the HBM2E controller always performs a precharge after executing any command that has the auto-precharge aruser bit set.
  • RDAP_HINT mode, in which the controller determines when to issue an auto-precharge command, based on user-issued auto-precharge input and the target address of the command.
User Write Auto-Precharge Policy Controls the amount of freedom that the controller has when handling auto-precharge requests. FORCED indicates that the controller follows the user auto-precharge request exactly. HINT indicates that the controller may override the auto-precharge request by disabling it when a page hit is detected (that is, if it receives two commands, one with auto-precharge and one without auto-precharge to the same page, the controller changes auto-precharge for the first to 0 so that the second can access the page without reopening it). You can issue a precharge request together with the write by asserting awuser[0]. You can choose between two values for this parameter:
  • WRAP_FORCED mode, in which the HBM2E controller always performs a precharge after executing any command that has the auto-precharge awuser bit set.
  • WRAP_HINT mode, in which the controller determines when to issue an auto-precharge command, based on user-issued auto-precharge input and the target address of the command.
Power Down Enable Causes the controller to power down when idle.
Figure 10. Group: General / Temperature Based Throttling
Table 8.  Group: General / Temperature Based Throttling
Display Name Description
Enable interface throttling based on temperature Enables temperature-based throttling where the desired throttling ratio can be specified for 2 temperature ranges: 85 to 94 degrees Celsius and 95 to 105 degrees Celsius. The throttling ratio for the 95 to 105 degree range should be greater than or equal to the ratio specified for the 85 to 94 degree range. No throttling is applied below 85 degrees and 100% throttling is applied above 105 degrees.
85C - 94C This parameter defines the throttle ratio as a percentage (0: no throttling, 100: full throttling) to be applied when the DRAM temperature is between 85 and 94 degrees Celsius.
> 95C This parameter defines the throttle ratio as a percentage (0: no throttling, 100: full throttling) that will be applied when the DRAM temperature is between 95 and 105 degrees Celsius.
Figure 11. Group: General/Data Configuration
Table 9.  Group: General / Data Configuration
Display Name Description
Enable pseudo BL8 mode If enabled, data access granularity is 64B (64 bits per pseudo-channel at BL8) which makes the most efficient use of the NoC and of the controller's command scheduling mechanism. Otherwise data access granularity is 32B (64 bits perpseudo-channel at BL4). The controller uses one or two memory bursts per 64B AXI command, based on this setting.
Data mode Specifies the HBM2E DM pin function and use of HBM ECC data bits.
  • In 256 bit mode, the DM pins and HBM ECC bits are not used at all. The AXI write strobes are ignored.
  • In 256 bit with ECC mode, the DM pins are used to transfer HBM ECC bits, and the HBM controller implements ECC generation and checking.
  • In 256 bit with data mask mode, the AXI write strobes are used to drive the DM pins.
  • In 288 bit mode, the HBM ECC bits are directly accessible to the user design, as AXI user bits. They can be used for data or a user-defined ECC scheme. In this mode the AXI write strobes are ignored.
Figure 12. Group: General / Pseudo-Channel n Power Estimation
Table 10.  Group: General / Pseudo-Channel n Power Estimation
Display Name Description
Bandwidth Specify estimated DRAM bandwidth for this pseudo-channel.
Page hit rate Specify estimated DRAM page hit rate for traffic for this pseudo-channel.
Read ratio Specify estimated read ratio for this pseudo-channel. Read ratio is the percentage of DRAM read traffic over write traffic.
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