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1. About the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP User Guide
2. Introduction to High Bandwidth Memory
3. Intel Agilex® 7 M-Series HBM2E Architecture
4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP
5. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Interface
6. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Controller Performance
7. Document Revision History for High Bandwidth Memory (HBM2E) Interface Intel FPGA IP User Guide
A. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Intel® Quartus® Prime Software Flow
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5.5. User Accesses to the HBM2E Controller
The high-bandwidth memory controller (HBMC) user memory-mapped registers allow you to monitor the status of the HBMC.
The allocation of register offsets from the base of the channel's register space are as follows:
- Initialization control : 32’h0010
- Initialization status : 32’h0014
- Thermal Status : 32’h0100
- ECC Error counters (PC0) : 32’h0560
- ECC Error counters (PC1) : 32’h0860
These addresses are offsets from the start of the HBM channel's register block. Each HBM sideband NoC target provides access to the registers of two channels, at offsets 32'h0000 and 32'h10000 from the base address that you have set for the NoC target in your NoC initiator's address map.