High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP User Guide

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ID 773264
Date 4/21/2023
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Document Table of Contents
Document Table of Contents x
1. About the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP User Guide 2. Introduction to High Bandwidth Memory 3. Intel Agilex® 7 M-Series HBM2E Architecture 4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP 5. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Interface 6. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Controller Performance 7. Document Revision History for High Bandwidth Memory (HBM2E) Interface Intel FPGA IP User Guide A. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Intel® Quartus® Prime Software Flow
1. About the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP User Guide x
1.1. Release Information
2. Introduction to High Bandwidth Memory x
2.1. HBM2E in Intel Agilex® 7 M-Series Devices 2.2. HBM2E DRAM Structure 2.3. Intel Agilex® 7 HBM2E Features 2.4. Intel Agilex® 7 M-Series HBM2E Controller Features 2.5. Intel Agilex® 7 M-Series FPGA HBM2E IP Device Family Support
3. Intel Agilex® 7 M-Series HBM2E Architecture x
3.1. Intel Agilex® 7 M-Series HBM2E Introduction 3.2. Intel Agilex® 7 M-Series Hard Memory NoC Subsystem 3.3. Address Mapping of the HBM2E Targets 3.4. Intel Agilex® 7 M-Series UIB Architecture 3.5. Intel Agilex® 7 M-Series HBM2E Controller Architecture
3.5. Intel Agilex® 7 M-Series HBM2E Controller Architecture x
3.5.1. Intel Agilex® 7 M-Series HBM2E Controller Details
4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP x
4.1. Creating an Intel® Quartus® Prime Pro Edition Project for High Bandwidth Memory (HBM2E) Interface FPGA IP 4.2. Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP
4.2. Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP x
4.2.1. General Parameters for High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP 4.2.2. Example Design Parameters for High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP 4.2.3. Modifying Your Pin Assignments to Choose the Physical Location of the HBM2E Device
5. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Interface x
5.1. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP High Level Block Diagram 5.2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Controller Interface Signals 5.3. User AXI Interface Timing 5.4. Platform Designer-Only Interface 5.5. User Accesses to the HBM2E Controller
5.2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Controller Interface Signals x
5.2.1. Reset, Clock, and Calibration Status Signals 5.2.2. 'Do not connect' Signals 5.2.3. Asynchronous HBM2E Controller Signals 5.2.4. AXI4 Interface Signals 5.2.5. AXI4-Lite Interface
5.3. User AXI Interface Timing x
5.3.1. AXI Write Transaction 5.3.2. AXI Read Transaction
5.5. User Accesses to the HBM2E Controller x
5.5.1. Initialization Control Register and Initialization Status Register 5.5.2. Thermal Status Register 5.5.3. ECC Error Counters Register 5.5.4. Error Login Registers
6. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Controller Performance x
6.1. High Bandwidth Memory (HBM2E) DRAM Bandwidth 6.2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Efficiency 6.3. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Latency 6.4. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Timing
A. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Intel® Quartus® Prime Software Flow x
A.1. Initiators Placement Recommendations A.2. Simulating HBM2E User Designs
1. About the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP User Guide
2. Introduction to High Bandwidth Memory
3. Intel Agilex® 7 M-Series HBM2E Architecture
4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP
5. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Interface
6. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Controller Performance
7. Document Revision History for High Bandwidth Memory (HBM2E) Interface Intel FPGA IP User Guide
A. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Intel® Quartus® Prime Software Flow

A.1. Initiators Placement Recommendations

Use the Interface Planner to modify the default physical placement of initiators. You can also use this tool to specify the placements of the UIB blocks, such as the HBM2E controller.

It is your responsibility to ensure that any placements that you specify are consistent with each other.

Follow these steps to change the locations of initiators:

  1. Launch the Intel® Quartus® Prime Pro Edition software.
  2. Click Tools > Interface Planner. The Interface Planner appears.
  3. On the Flow tab, click Initialize Interface Planner.
  4. On the Plan tab, you can see the different modules of HBM2E IP under the ed_synth hierarchy. To choose the correct location of the HBM2E instance, right-click the HBM controller instance and select Generate Legal Locations of Selected Element. The system reports the legal locations at which you can place your HBM controller.
    For each instance, there are two legal locations at which you can place the controller: top or bottom. Right-click the location where you want to place the controller and click Place at Selected. The following figure shows the bottom controller selected:
  5. Once the HBM2E controller is placed, click Autoplace Fixed three times to fix the locations of the UIB PHY, targets, and NoC clock control block based on the controller location. By this step, you see all the instances of your HBM2E IP and NoC clock control that have been placed.
  6. To assign physical locations to the initiators in your design, right-click an initiator and select Generate Legal Locations for Selected Element. The system displays all legal locations for the selected initiator.
    Select the location at which you want to place the initiator. (Refer to Guidelines for Assigning Physical Locations to Initiators, below.)

Guidelines for Assigning Physical Locations to Initiators

For information on the available initiators in the bottom and top hard memory NoC and how they span the sectors relative to the physical UIB location, refer to the NoC User Guide or the NoC techmodule. Note that all HBM targets are placed within the three sectors directly beneath the UIB.

When placing initiators, you should consider the following points:

  • The desired initiator–target connectivity.
  • The physical arrangement of the targets. (Refer to the table, below.)
    Table 43.  Target Placements
    Top
    UIB - Left UIB - Middle UIB - Right
    tniu_ch5_u1 tniu_ch7_u1 tniu_ch4_u1 tniu_ch6_u1 tniu_ch5_u0 tniu_ch7_u0 tniu_ch4_u0 tniu_ch6_u0 tniu_ch1_u1 tniu_ch3_u1 tniu_ch0_u1 tniu_ch2_u1 tniu_ch1_u0 tniu_ch3_u0 tniu_ch0_u0 tniu_ch2_u0
     
    Bottom
    UIB - Left UIB - Middle UIB - Right
    tniu_ch2_u0 tniu_ch0_u0 tniu_ch3_u0 tniu_ch1_u0 tniu_ch2_u1 tniu_ch0_u1 tniu_ch3_u1 tniu_ch1_u1 tniu_ch6_u0 tniu_ch4_u0 tniu_ch7_u0 tniu_ch5_u0 tniu_ch6_u1 tniu_ch4_u1 tniu_ch7_u1 tniu_ch5_u1
  • When choosing physical locations for initiators, follow these recommendations:
    • If initiators and targets are to be connected one-to-one, place the initiators closest to the targets.
    • For a design containing sixteen initiators, select nine initiators from the three sectors directly beneath the UIB, and three initiators from the sector adjacent to the UIB on the left, and four initiators from the sectors adjacent to UIB on the right.
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