High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP User Guide

ID 773264
Date 4/21/2023
Public

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5.2.2. 'Do not connect' Signals

The following HBM2E memory signals represent physical connections between the UIB and HBM2E device, and must not be connected in your design. Your design must route these signals to its top level, and leave them unconnected.
Table 18.  "Do not connect" Thermal Status Signals
Signal Direction Description
hbm_cattrip_i Input Physical Device Catastrophic Trip (CATTRIP) output from the HBM2E device to the HBM controller; leave unconnected in your design.
hbm_temp_i Input[2:0] Physical temperature readout from the HBM2E device to the HBM controller; leave unconnected in your design.