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1. About the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP User Guide
2. Introduction to High Bandwidth Memory
3. Intel Agilex® 7 M-Series HBM2E Architecture
4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP
5. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Interface
6. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Controller Performance
7. Document Revision History for High Bandwidth Memory (HBM2E) Interface Intel FPGA IP User Guide
A. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Intel® Quartus® Prime Software Flow
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6.1. High Bandwidth Memory (HBM2E) DRAM Bandwidth
For each HBM2E DRAM in an Intel Agilex® 7 device, there are eight channels of 128-bits each. The following example illustrates the calculation of bandwidth offered by one HBM2E interface.
Assuming an interface running at 1.6 GHz: 128 DQ × 1.6 GHz = 204.8 Gbps
- The interface operates in double data-rate mode, so the total bandwidth per HBM2E is: 204.8 Gbps × 2 = 409.6 Gbps.
- The total bandwidth for the HBM2E interface is: 409.6 Gbps × 8 channels = 409.6 GByte/sec.
- If the HBM2E controller operates at 90% efficiency, the effective bandwidth is: 409.6 GByte/sec × 0.9 = ~368 GByte/sec.