These per-pseudo-channel registers log the first error on the read/write command. Error data is held by hardware until you clear the lock bit on the register.
To access the write register for Log 0, Log 1, Log 2, or Log 3, issue the read command to the offset 0x540h/0x544/0x548/0x54C for pseudo-channel 0 and 0x840/0x844/0x848/0x84C for pseudo-channel 1.
To access the read register for Log 0, Log 1, Log 2, or Log 3, issue the read command to the offset 0x550h/0x554/0x558/0x55C for pseudo-channel 0 and 0x850/0x854/0x858/0x85C for pseudo-channel 1.
Table 35. Write Command Log 0 Register
Bits |
Access |
Default |
Name |
Description |
14:0 |
RO |
15'b0 |
AWID |
Write ID for the error transaction. |
15 |
RO |
1'b0 |
Reserved. |
Reserved bits. |
23:16 |
RO |
8'b0 |
AWLEN |
Write Burst length for the error transaction. |
26:24 |
RO |
3'b0 |
AWSIZE |
Write Burst size for the error transaction. |
28:27 |
RO |
2'b0 |
AWBURST |
Write Burst type for the error transaction. |
29 |
RO |
1'b0 |
AWLOCK |
Write Lock type for the error transaction. |
31:30 |
RO |
2'b0 |
Reserved. |
Reserved bits. |
Table 36. Write Command Log 1 Register
Bits |
Access |
Default |
Name |
Description |
31:0 |
RO |
32'b0 |
AWADDR_LO |
Lower 32-bits of write address for the error transaction. |
Table 37. Write Command Log 2 Register
Bits |
Access |
Default |
Name |
Description |
31:0 |
RO |
32'b0 |
AWADDR_HI |
Upper 32-bits of write address for the error transaction. |
Table 38. Write Command Log 3 Register
Bits |
Access |
Default |
Name |
Description |
2:0 |
RO |
3'b0 |
AWPROT |
Write protection type for the error transaction. |
6:3 |
RO |
4'b0 |
AWQOS |
Write QOS for the error transaction. |
30:7 |
RO |
24'b0 |
Reserved. |
Reversed bits. |
31 |
RW1C |
1'b0 |
R_AWHDRLOG_LOCK |
This bit is set when 0540h/0840h- 054Fh/084Fh registers are captured. Software write 1 to clears it. |
Table 39. Read Command Log 0 Register
Bits |
Access |
Default |
Name |
Description |
14:0 |
RO |
15'b0 |
ARID |
Read ID for the error transaction. |
15 |
RO |
1'b0 |
Reserved. |
Reserved bits. |
23:16 |
RO |
8'b0 |
ARLEN |
Read Burst length for the error transaction. |
26:24 |
RO |
3'b0 |
ARSIZE |
Read Burst size for the error transaction. |
28:27 |
RO |
2'b0 |
ARBURST |
Read Burst type for the error transaction. |
29 |
RO |
1'b0 |
ARLOCK |
Read Lock type for the error transaction. |
31:30 |
RO |
2'b0 |
Reserved. |
Reserved bits. |
Table 40. Read Command Log 1 Register
Bits |
Access |
Default |
Name |
Description |
31:0 |
RO |
32'b0 |
ARADDR_LO |
Lower 32-bits of read address for the error transaction. |
Table 41. Read Command Log 2 Register
Bits |
Access |
Default |
Name |
Description |
31:0 |
RO |
32'b0 |
ARADDR_HI |
Upper 32-bits of read Address for the error transaction. |
Table 42. Read Command Log 3 Register
Bits |
Access |
Default |
Name |
Description |
2:0 |
RO |
3'b0 |
ARPROT |
Read protection type for the error transaction. |
6:3 |
RO |
4'b0 |
ARQOS |
Read QOS for the error transaction. |
30:7 |
RO |
24'b0 |
Reserved. |
Reserved bits. |
31 |
RW1C |
1'b0 |
R_ARHDRLOG_LOCK |
This bit is set when 0550h/0850h- 055Fh/085Fh registers are captured. Software clears it. |