Intel Agilex® 7 LVDS SERDES User Guide: F-Series and I-Series

Download PDF
ID 721819
Date 12/11/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Overview 2. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Architecture 3. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Transmitter 4. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Receiver 5. Intel Agilex® 7 F-Series and I-Series High-Speed LVDS I/O Implementation Guide 6. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Timing 7. LVDS SERDES Intel® FPGA IP Design Examples 8. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Design Guidelines 9. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Troubleshooting Guidelines 10. Documentation Related to the Intel Agilex® 7 LVDS SERDES User Guide: F-Series and I-Series 11. Document Revision History for the Intel Agilex® 7 LVDS SERDES User Guide: F-Series and I-Series
1. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Overview x
1.1. LVDS SERDES Usage Modes
2. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Architecture x
2.1. F-Series and I-Series GPIO Banks, SERDES, and DPA Locations 2.2. SERDES Blocks, Modes, and Clock Domains
3. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Transmitter x
3.1. LVDS SERDES Transmitter Blocks 3.2. Serializer 3.3. Differential I/O Bit Position 3.4. Clocking the Differential Transmitters
3.2. Serializer x
3.2.1. Serializer Bypass for DDR and SDR Operations
3.4. Clocking the Differential Transmitters x
3.4.1. Transmitter Output Clock Parameters Settings
3.4.1. Transmitter Output Clock Parameters Settings x
3.4.1.1. Edge-Aligned tx_outclock to tx_out 3.4.1.2. Center-Aligned tx_outclock to tx_out
4. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Receiver x
4.1. LVDS SERDES Receiver Blocks 4.2. Clocking the LVDS SERDES Receivers 4.3. LVDS SERDES Receiver Modes
4.1. LVDS SERDES Receiver Blocks x
4.1.1. Dynamic Phase Alignment Block 4.1.2. Synchronizer (DPA FIFO) 4.1.3. Data Realignment Block (Bit Slip) 4.1.4. Deserializer
4.2. Clocking the LVDS SERDES Receivers x
4.2.1. Receiver Input Clock Parameters Settings
4.2.1. Receiver Input Clock Parameters Settings x
4.2.1.1. Edge-Aligned inclock to rx_in 4.2.1.2. Center-Aligned inclock to rx_in
4.3. LVDS SERDES Receiver Modes x
4.3.1. Non-DPA Mode 4.3.2. DPA Mode 4.3.3. Soft-CDR Mode
5. Intel Agilex® 7 F-Series and I-Series High-Speed LVDS I/O Implementation Guide x
5.1. LVDS SERDES Intel® FPGA IP 5.2. LVDS Interface with External PLL Mode 5.3. LVDS SERDES IP Initialization and Reset
5.1. LVDS SERDES Intel® FPGA IP x
5.1.1. Release Information 5.1.2. LVDS SERDES Intel® FPGA IP Features 5.1.3. LVDS SERDES IP Usage Modes 5.1.4. Generating the LVDS SERDES Intel® FPGA IP 5.1.5. LVDS SERDES Intel® FPGA IP Parameter Settings 5.1.6. LVDS SERDES Intel® FPGA IP Signals
5.1.4. Generating the LVDS SERDES Intel® FPGA IP x
5.1.4.1. Intel® FPGA IP Generation Output
5.1.5. LVDS SERDES Intel® FPGA IP Parameter Settings x
5.1.5.1. LVDS SERDES Intel® FPGA IP General Settings 5.1.5.2. LVDS SERDES Intel® FPGA IP PLL Settings 5.1.5.3. LVDS SERDES Intel® FPGA IP Receiver Settings 5.1.5.4. LVDS SERDES Intel® FPGA IP Transmitter Settings 5.1.5.5. LVDS SERDES Intel® FPGA IP Clock Resource Summary
5.2. LVDS Interface with External PLL Mode x
5.2.1. IOPLL IP Signal Interface with LVDS SERDES IP 5.2.2. IOPLL Parameter Values for External PLL Mode 5.2.3. Connection between IOPLL IP and LVDS SERDES IP in External PLL Mode
5.3. LVDS SERDES IP Initialization and Reset x
5.3.1. Initializing the LVDS SERDES IP in Non-DPA Mode 5.3.2. Initializing the LVDS SERDES IP in DPA Mode 5.3.3. Resetting the DPA 5.3.4. Word Boundaries Alignment
5.3.4. Word Boundaries Alignment x
5.3.4.1. Aligning Word Boundaries
6. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Timing x
6.1. LVDS SERDES Intel® FPGA IP Timing 6.2. LVDS SERDES Source-Synchronous Timing Budget
6.1. LVDS SERDES Intel® FPGA IP Timing x
6.1.1. I/O Timing Analysis 6.1.2. FPGA Timing Analysis 6.1.3. Timing Analysis for the External PLL Mode
6.1.1. I/O Timing Analysis x
6.1.1.1. Obtaining RSKM Report 6.1.1.2. Obtaining TCCS Report
6.2. LVDS SERDES Source-Synchronous Timing Budget x
6.2.1. Transmitter Channel-to-Channel Skew 6.2.2. Receiver Skew Margin
7. LVDS SERDES Intel® FPGA IP Design Examples x
7.1. LVDS SERDES IP Synthesizable Intel® Quartus® Prime Design Examples 7.2. LVDS SERDES IP Simulation Design Example
8. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Design Guidelines x
8.1. Use PLLs in Integer PLL Mode for LVDS 8.2. Use High-Speed Clock from PLL to Clock SERDES Only 8.3. Pin Placement for Differential Channels 8.4. SERDES Pin Pairs for Soft-CDR Mode 8.5. Placing LVDS Transmitters and Receivers in the Same GPIO Bank
1. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Overview
2. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Architecture
3. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Transmitter
4. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Receiver
5. Intel Agilex® 7 F-Series and I-Series High-Speed LVDS I/O Implementation Guide
6. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Design Guidelines
9. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Troubleshooting Guidelines
10. Documentation Related to the Intel Agilex® 7 LVDS SERDES User Guide: F-Series and I-Series
11. Document Revision History for the Intel Agilex® 7 LVDS SERDES User Guide: F-Series and I-Series

5.1.5.3. LVDS SERDES Intel® FPGA IP Receiver Settings

The parameter options in the Receiver Settings tab are available if you select the RX Non-DPA, RX DPA-FIFO, or RX Soft-CDR functional mode in the General Settings tab.
Table 16.  Receiver Settings Tab—Bitslip Settings
Parameter Value Description
Enable bitslip mode
  • On
  • Off

Turn on to add a bit slip block to the receiver data path and expose the rx_bitslip_ctrl port (one input per channel).

Default is Off.

Every assertion of the rx_bitslip_ctrl signal adds one bit of serial latency to the data path of the specified channel.

Note: You must enable this parameter for the IP simulation driver to function correctly.
Enable rx_bitslip_reset port
  • On
  • Off

Turn on to expose the rx_bitslip_reset port (one input per channel) that you can use to reset the bit slip.

Default is Off.

This setting is available if you turn on Enable bitslip mode.

Enable rx_bitslip_max port
  • On
  • Off

Turn on to expose the rx_bitslip_max port (one output per channel).

Default is Off.

When asserted, the next rising edge of rx_bitslip_ctrl resets the latency of the bit slip to zero.

This setting is available if you turn on Enable bitslip mode.

Bitslip rollover value Deserialization factor

Specifies the maximum latency that the bit slip can inject.

When the bit slip reaches the specified value, it rolls over and the rx_bitslip_max signal asserts.

The rollover value is set automatically to the deserialization factor.
Table 17.  Receiver Settings Tab—DPA Settings
Parameter Value Description
Enable rx_dpa_reset port
  • On
  • Off

Turn on to expose the rx_dpa_reset port that you can use to reset the DPA logic of each channel independently.

(Formerly known as rx_reset.)

Default is Off.

This setting is available if you select RX DPA-FIFO or RX Soft-CDR in Functional mode.

Enable rx_fifo_reset port
  • On
  • Off

Turn on to use your logic to drive the rx_fifo_reset port to reset the DPA-FIFO block.

Default is Off.

This setting is available if you select RX DPA-FIFO in Functional mode.

Enable rx_dpa_hold port
  • On
  • Off

Turn on to expose the rx_dpa_hold input port (one input per channel).

If set high, the DPA logic in the corresponding channel does not switch sampling phases.

(Formerly known as rx_dpll_hold.)

Default is Off.

This setting is available if you select RX DPA-FIFO in Functional mode.

Enable DPA loss of lock on one change
  • On
  • Off
  • On—the IP drives the rx_dpa_locked signal low when the DPA changes phase selection from the initially locked position. When the DPA changes the phase selection back to the initial locked position, the IP drives the rx_dpa_locked signal high.
  • Off—the IP drives the rx_dpa_locked signal low when the DPA moves two phases in the same direction away from the initial locked position. When the DPA changes the phase selection to be within one phase or same phase as the initial locked position, the IP drives the rx_dpa_locked signal high.

Default is Off.

Deassertion of rx_dpa_locked does not indicate that the data is invalid. Instead, the deassertion indicates that the DPA has changed phase taps to track variations between the inclock and rx_in data.

This setting is available if you select RX DPA-FIFO or RX Soft-CDR in Functional mode.

Intel recommends that you use data checkers to verify data accuracy.

Enable DPA alignment only to rising edges of data
  • On
  • Off
  • On—DPA logic counts only the rising edges of the incoming serial data
  • Off—DPA logic counts the rising and falling edges

Default is Off.

This setting is available if you select RX DPA-FIFO or RX Soft-CDR in Functional mode.

Note: Intel recommends that you use this port only for high jitter systems and turn it off for typical applications.
(Simulation only) Specify PPM drift on the recovered clock(s) — Specifies the amount of phase drift the LVDS SERDES IP simulation model adds to the recovered rx_divfwdclks.
Note: This feature will be supported in a future version of the Intel® Quartus® Prime software.
Table 18.  Receiver Settings Tab—Non-DPA Settings
Parameter Value Description
Desired receiver inclock phase shift (degrees) —

Specifies, in degrees of the LVDS fast clock, the ideal phase delay of inclock with respect to transitions in the incoming serial data.

For example, specifying 180° implies that the inclock is center aligned to the incoming data.

Actual receiver inclock phase shift (degrees)

Depends on the fast_clock and inclock frequencies. Refer to the related information.

Specifies the closest achievable receiver inclock phase shift to the desired receiver inclock phase shift.

RCCS (ps) —

Specifies the RCCS value in picoseconds.

Depending on the order the Intel® Quartus® Prime software reads the project .sdc files, this value may override any RCCS value you specify in the .sdc file.

To avoid uncertainty, Intel recommends that you specify the RCCS value in only one of the locations.

Related Information
Level Two Title