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1. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Overview
2. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Architecture
3. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Transmitter
4. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Receiver
5. Intel Agilex® 7 F-Series and I-Series High-Speed LVDS I/O Implementation Guide
6. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Design Guidelines
9. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Troubleshooting Guidelines
10. Documentation Related to the Intel Agilex® 7 LVDS SERDES User Guide: F-Series and I-Series
11. Document Revision History for the Intel Agilex® 7 LVDS SERDES User Guide: F-Series and I-Series
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1.1. LVDS SERDES Usage Modes
You can use the F-Series and I-Series LVDS SERDES through the LVDS SERDES Intel® FPGA IP. The LVDS SERDES IP supports four SERDES functional modes.
Functional Mode | Description |
---|---|
Transmitter (TX) |
|
Non-DPA receiver (RX Non-DPA) |
|
DPA-FIFO receiver (RX DPA-FIFO) |
|
Soft-CDR receiver (RX Soft-CDR) |
|
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