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1. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Overview
2. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Architecture
3. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Transmitter
4. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Receiver
5. Intel Agilex® 7 F-Series and I-Series High-Speed LVDS I/O Implementation Guide
6. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Design Guidelines
9. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Troubleshooting Guidelines
10. Documentation Related to the Intel Agilex® 7 LVDS SERDES User Guide: F-Series and I-Series
11. Document Revision History for the Intel Agilex® 7 LVDS SERDES User Guide: F-Series and I-Series
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5.1.5.5. LVDS SERDES Intel® FPGA IP Clock Resource Summary
The Clock Resource Summary tab lists the required frequencies, phase shifts, duty cycles of the required clocks, instructions for connections, and compensation mode that you need to set in the IOPLL Intel® FPGA IP.
Configuration | Description |
---|---|
PLL VCO | Specifies the frequency that you need to set to the Desired VCO Frequency parameter in the IOPLL IP. |
Fast clock | Specifies the frequency, phase shift, duty cycle that you need to set for lvds_clk[1:0] ports in the IOPLL IP. |
Load enable | Specifies the frequency, phase shift, duty cycle that you need to set for loaden[1:0] ports in the IOPLL IP. |
Core clock | Specifies the frequency, phase shift, duty cycle that you need to set for any PLL output clock from the IOPLL IP that is used for core clock connection. |
Compensation Mode | Specifies the option you should select for the Compensation Mode parameter in the IOPLL IP. |