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1. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Overview
2. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Architecture
3. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Transmitter
4. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Receiver
5. Intel Agilex® 7 F-Series and I-Series High-Speed LVDS I/O Implementation Guide
6. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Design Guidelines
9. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Troubleshooting Guidelines
10. Documentation Related to the Intel Agilex® 7 LVDS SERDES User Guide: F-Series and I-Series
11. Document Revision History for the Intel Agilex® 7 LVDS SERDES User Guide: F-Series and I-Series
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5.1.3. LVDS SERDES IP Usage Modes
You can implement four usage modes using the LVDS SERDES IP.
- Transmitter—select the TX option to generate the IP as a transmitter.
- Non-DPA receiver—select the RX Non-DPA option to generate the IP as non-DPA receiver.
- DPA receiver—select the RX DPA-FIFO option to generate the IP as DPA receiver.
- Soft CDR receiver—select the RX Soft-CDR option to generate the IP as soft-CDR receiver.
Each GPIO sub-bank can support one IP instance with a maximum of 12 transmitter and 12 receiver channels. For designs with more than 12 channels, you must generate a new LVDS SERDES IP instance and place it in a new GPIO sub-bank.
Number of Channels | Usage Modes | PLL Configuration | Number of IP Instances |
---|---|---|---|
1–24
Maximum channels:
|
Transmitters and receivers | External PLL | 2 |
1–12 | Transmitters | External PLL | 1 |
Internal PLL | 1 | ||
1–12 | Receivers | External PLL | 1 |
Internal PLL | 1 |