F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide

Download PDF
ID 720987
Date 4/01/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide 2. Quick Start Guide 3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example 4. Interface Signals Description 5. Configuration Registers Description 6. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design 2.3. Compiling and Simulating the Design 2.4. Compiling and Testing the Design in Hardware
2.2. Generating the Design x
2.2.1. Procedure 2.2.2. Design Example Parameters
2.3. Compiling and Simulating the Design x
2.3.1. Procedure 2.3.2. Testbench
2.4. Compiling and Testing the Design in Hardware x
2.4.1. Procedure 2.4.2. Hardware Setup
3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing 3.6. Interface Signals 3.7. Configuration Registers
3.3. Functional Description x
3.3.1. Design Components 3.3.2. Clocking Scheme 3.3.3. Reset Scheme
3.4. Simulation x
3.4.1. Test Case
3.5. Hardware Testing x
3.5.1. Test Procedure
4. Interface Signals Description x
4.1. Clock and Reset Interface Signals 4.2. Avalon® Memory-Mapped Interface Signals 4.3. Avalon® Streaming Interface Signals 4.4. PHY Interface Signals 4.5. Status Interface
5. Configuration Registers Description x
5.1. Register Access Definition 5.2. Low Latency Ethernet 10G MAC 5.3. PHY
5.3. PHY x
5.3.1. 1G/2.5G/5G/10G Multi-rate PHY
1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
4. Interface Signals Description
5. Configuration Registers Description
6. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide

2.3.1. Procedure

You can compile and simulate the design by running a simulation script from the command prompt.
  1. Navigate to the LL10G_10G_USXGMII folder in your design example: cd <your_design_path>/LL10G_10G_USXGMII.
  2. Run the following command: quartus_tlg altera_eth_top.
  3. Copy the generated .mif file to the sim directory: cp <your_design_path>/LL10G_10G_USXGMII/altera_eth_top_tiles_z1577a_x0_y166_n0.mif simulation/ed_sim/setup_scripts/.
  4. Navigate to the sim directory: cd simulation/ed_sim/setup_sripts/.
  5. Run the following command: ip-setup-simulation -quartus-project=../../../altera_eth_top.qpf
  6. To run the test bench, run one of the following commands, depending on the simulator you are using.
  7. At the command prompt, change the working directory to <Example Design>\simulation\ed_sim\<Simulator> .
  8. Run the simulation script for the simulator of your choice.
    Simulator Working Directory Command
    VCS* <Example Design>/simulation/ed_sim/synopsys/vcs sh altera_tb_run.sh
A successful simulation ends with the following message: 
Simulation passed.
After successful completion, you can analyze the results.
Level Two Title