F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide

ID 720987
Date 4/01/2022
Public

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4.1. Clock and Reset Interface Signals

Table 9.  Clock and Reset Interface Signals
Signal Direction Width Description
csr_clk In 1 125 MHz configuration clock for the Avalon® memory-mapped interface and core logic.
i_reconfig_reset In 1 Active-low reset signal for the Avalon® memory-mapped interface.
i_tx_rst_n In 1 Active-low reset signal for the TX datapath.
i_rx_rst_n In 1 Active-low reset signal for the RX datapath.

mac64b_clk

mac32b_clk

Out 1 156.25 MHz configuration clock for the Avalon® streaming interface and 0 ppm frequency difference with refclk.
refclk_10g In 1 125 MHz reference clock for the TX PLLs.
reset In 1 Assert this asynchronous and active-high signal to reset the whole design example.
tx_digitalreset Out [NUM_CHANNELS] Asynchronous and active-high signal to reset PCS TX portion of the transceiver PHY.
rx_digitalreset Out [NUM_CHANNELS] Asynchronous and active-high signal to reset PCS RX portion of the transceiver PHY.