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1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
4. Interface Signals Description
5. Configuration Registers Description
6. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
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4.4. PHY Interface Signals
Signal | Direction | Width | Description |
---|---|---|---|
rx_serial_data | In | 2 | RX serial input data |
tx_serial_data | Out | 2 | TX serial output data |