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1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
4. Interface Signals Description
5. Configuration Registers Description
6. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
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3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
The 10M/100M/1G/2.5G/5G/10G (USXGMII) design example demonstrates an Ethernet solution for Intel® Agilex™ (F-tile) devices using the LL 10GbE MAC Intel® FPGA IP operating at 10M, 100M, 1G, 2.5G, 5G, and 10G.
Generate the design example from the Example Design tab of the LL 10GbE Intel® FPGA IP parameter editor.