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1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
4. Interface Signals Description
5. Configuration Registers Description
6. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
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3.2. Hardware and Software Requirements
Intel uses the following hardware and software to test the design example in a Linux system:
- Intel® Quartus® Prime Pro Edition software
- VCS simulator
- For hardware testing:
- Intel® Agilex™ I-Series Transceiver-SoC Development Kit (AGIB027R31B1E2VR0)
- QSFP-DD Loopback Module connected to J27(QSFP-DD Connector). Intel uses Amphenol QSFP-DD 400G LOOPBACK ADAPTER MODULE 0dB (SF-NLNAMB0001-0001) for hardware test.