F-Tile Dynamic Reconfiguration Design Example User Guide

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ID 710582
Date 4/03/2023
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for CPRI Multirate Design Example 3. Detailed Description for PMA/FEC Direct PHY Multirate Design Example 4. Detailed Description for Ethernet Multirate Design Example 5. Detailed Description for Ethernet to CPRI Design Example 6. F-Tile Dynamic Reconfiguration Design Example User Guide Archives 7. Document Revision History for F-Tile Dynamic Reconfiguration Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Compiling the Compilation-Only Project 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
1.2. Generating the Design x
1.2.1. CPRI Multirate Design Example Parameters 1.2.2. Ethernet Multirate Design Example Parameters 1.2.3. PMA/FEC Direct PHY Multirate Design Example Parameters 1.2.4. Ethernet to CPRI Design Example Parameters
2. Detailed Description for CPRI Multirate Design Example x
2.1. CPRI Multirate Design Example: Functional Description 2.2. CPRI Multirate Design Example: Registers
2.1. CPRI Multirate Design Example: Functional Description x
2.1.1. CPRI Multirate Design Example: Simulation Testbench 2.1.2. CPRI Multirate Hardware Design Example 2.1.3. CPRI Multirate Design Example: Reset Scheme
3. Detailed Description for PMA/FEC Direct PHY Multirate Design Example x
3.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description 3.2. PMA/FEC Direct PHY Multirate Design Example: Registers
3.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description x
3.1.1. PMA/FEC Direct PHY Multirate Design Example: Simulation Testbench 3.1.2. PMA/FEC Direct PHY Multirate Hardware Design Example
4. Detailed Description for Ethernet Multirate Design Example x
4.1. Ethernet Multirate Design Example: Functional Description 4.2. Ethernet Multirate Design Example: Registers
4.1. Ethernet Multirate Design Example: Functional Description x
4.1.1. Ethernet Multirate Design Example: Simulation Testbench 4.1.2. Ethernet Multirate Hardware Design Example
5. Detailed Description for Ethernet to CPRI Design Example x
5.1. Ethernet to CPRI Design Example: Functional Description 5.2. Ethernet to CPRI Design Example: Registers
5.1. Ethernet to CPRI Design Example: Functional Description x
5.1.1. Ethernet to CPRI Dynamic Reconfiguration Design Example: Simulation Testbench 5.1.2. Ethernet to CPRI Dynamic Reconfiguration Hardware Design Example
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
4. Detailed Description for Ethernet Multirate Design Example
5. Detailed Description for Ethernet to CPRI Design Example
6. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
7. Document Revision History for F-Tile Dynamic Reconfiguration Design Example User Guide

1. Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 23.1

The F-Tile Dynamic Reconfiguration IP provides a simulation testbench and hardware design example that supports compilation and simulation. When you generate the design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.

Intel® also provides a compilation-only example project that you can use to quickly estimate IP core area and timing.

Figure 1. Development Steps for the Design Example
The F-Tile Dynamic Reconfiguration design example supports the following design variants:
Table 1.  Supported Design Example Variants
Protocol Base Variant Target Variants
CPRI 24G CPRI with RS-FEC 1.2G CPRI
2.4G CPRI
3G CPRI
4.9G CPRI
6G CPRI
9.8G CPRI
10G CPRI
10G CPRI with RS-FEC
12G CPRI
12G CPRI with RS-FEC
24G CPRI
24G CPRI with RS-FEC
Ethernet 100G-4 with RS-FEC 100G-4 with RS-FEC
100G-4
100G-2 with RS-FEC
2x50G-1 with RS-FEC
4x25G-1 with RS-FEC
4x25G-1
25G-1 with RS-FEC 25G-1 with RS-FEC
10G-1
400G-8 with RS-FEC 400G-8 with RS-FEC
2x200G-4 with RS-FEC
4x100G-2 with RS-FEC
100G-4 with RS-FEC and PTP 1 100G-4 with RS-FEC and PTP
100G-4 with PTP
100G-2 with RS-FEC and PTP
2x50G-1 with RS-FEC and PTP
4x25G-1 with RS-FEC and PTP
4x25G-1 with PTP
25G-1 with RS-FEC and PTP 2 25G-1 with RS-FEC and PTP
10G-1 with PTP
400G-8 with RS-FEC and PTP2 400G-8 with RS-FEC and PTP
2x200G-4 with RS-FEC and PTP
4x100G-2 with RS-FEC and PTP
FHT 400G-4 with RS-FEC FHT 400G-4 with RS-FEC
FHT 1x200G-4 with RS-FEC
FHT 2x200G-2 with RS-FEC
FHT 2x100G-2 with RS-FEC
FHT 4x100G-1 with RS-FEC
PMA/FEC Direct PHY 53.125G 53.125G
53.125G with RS-FEC
25.7815G
24.33024G
10.3125G
10.1376G
9.8304G
4.9152G
2.4576G
400G-8 with RS-FEC 1x400G-8 with RS-FEC (PAM4) FEC Direct (544,514)
2x200G-4 with RS-FEC (PAM4) FEC Direct (544,514)
2x100G-4 with RS-FEC (NRZ) FEC Direct (528,514)
Ethernet to CPRI 25G-1 with RS-FEC 25G-1 with RS-FEC
10G-1
24G CPRI with RS-FEC
10G CPRI
9.8G CPRI
4.9G CPRI
2.4G CPRI
25G-1 with RS-FEC (with 1GE) 25G-1 with RS-FEC
10G-1
1G-1
24G CPRI with RS-FEC
10G CPRI
9.8G CPRI
4.9G CPRI
2.4G CPRI

Section Content
Hardware and Software Requirements
Generating the Design
Directory Structure
Compiling the Compilation-Only Project
Simulating the Design Example Testbench
Compiling and Configuring the Design Example in Hardware
Testing the Hardware Design Example

Related Information
1 Basic Accuracy Mode
2 Advanced Accuracy Mode
Level Two Title