F-Tile Dynamic Reconfiguration Design Example User Guide

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ID 710582
Date 4/03/2023
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for CPRI Multirate Design Example 3. Detailed Description for PMA/FEC Direct PHY Multirate Design Example 4. Detailed Description for Ethernet Multirate Design Example 5. Detailed Description for Ethernet to CPRI Design Example 6. F-Tile Dynamic Reconfiguration Design Example User Guide Archives 7. Document Revision History for F-Tile Dynamic Reconfiguration Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Compiling the Compilation-Only Project 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
1.2. Generating the Design x
1.2.1. CPRI Multirate Design Example Parameters 1.2.2. Ethernet Multirate Design Example Parameters 1.2.3. PMA/FEC Direct PHY Multirate Design Example Parameters 1.2.4. Ethernet to CPRI Design Example Parameters
2. Detailed Description for CPRI Multirate Design Example x
2.1. CPRI Multirate Design Example: Functional Description 2.2. CPRI Multirate Design Example: Registers
2.1. CPRI Multirate Design Example: Functional Description x
2.1.1. CPRI Multirate Design Example: Simulation Testbench 2.1.2. CPRI Multirate Hardware Design Example 2.1.3. CPRI Multirate Design Example: Reset Scheme
3. Detailed Description for PMA/FEC Direct PHY Multirate Design Example x
3.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description 3.2. PMA/FEC Direct PHY Multirate Design Example: Registers
3.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description x
3.1.1. PMA/FEC Direct PHY Multirate Design Example: Simulation Testbench 3.1.2. PMA/FEC Direct PHY Multirate Hardware Design Example
4. Detailed Description for Ethernet Multirate Design Example x
4.1. Ethernet Multirate Design Example: Functional Description 4.2. Ethernet Multirate Design Example: Registers
4.1. Ethernet Multirate Design Example: Functional Description x
4.1.1. Ethernet Multirate Design Example: Simulation Testbench 4.1.2. Ethernet Multirate Hardware Design Example
5. Detailed Description for Ethernet to CPRI Design Example x
5.1. Ethernet to CPRI Design Example: Functional Description 5.2. Ethernet to CPRI Design Example: Registers
5.1. Ethernet to CPRI Design Example: Functional Description x
5.1.1. Ethernet to CPRI Dynamic Reconfiguration Design Example: Simulation Testbench 5.1.2. Ethernet to CPRI Dynamic Reconfiguration Hardware Design Example
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
4. Detailed Description for Ethernet Multirate Design Example
5. Detailed Description for Ethernet to CPRI Design Example
6. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
7. Document Revision History for F-Tile Dynamic Reconfiguration Design Example User Guide

5.1.1. Ethernet to CPRI Dynamic Reconfiguration Design Example: Simulation Testbench

The Ethernet to CPRI Dynamic Reconfiguration example design simulation testbench block diagrams are shown in the following figures:
Figure 28. Simulation Testbench Block Diagram for Ethernet to CPRI Dynamic Reconfiguration Design Example
Figure 29. Simulation Testbench Block Diagram for Ethernet to CPRI Dynamic Reconfiguration Design Example (with 1GE)
The testbench program controls the testbench components via Avalon® Memory-Mapped Interface access, status and control signals. The Avalon® Memory-Mapped Interface arbiter decodes the Avalon® Memory-Mapped Interface access from the testbench program into multiple Avalon® Memory-Mapped Interface slaves.
Simulation Flow:
  • Ethernet Multirate IP DUT is power-up based on base profile.
  • Initialize the testbench variables based on power-up profile. The parameter settings, located in the basic_avl_tb_top.sv file, are:
    • DR_NUM: To indicate the number of dynamic reconfiguration transitions.
    • DR_SEQ: To indicate the dynamic reconfiguration sequence.
  • Perform dynamic reconfiguration.
  • Start traffic test.
  • Check the testbench error flag and determine whether testbench passed or failed. The error flag is set to 1 if there is any error after dynamic reconfiguration traffic tests.

For customization, you can modify the DR_NUM and DR_SEQ localparam to configure the test flow. The profile ID is passed to the dynamic reconfiguration IP to configure the intended dynamic reconfiguration task.

For example, you want to achieve this Dynamic Reconfiguration sequence: Ethernet 25G-1 > CPRI 24G with RS-FEC > Ethernet 10G-1.

The localparams changes are:
  • Localparam DR_NUM = 2
  • Localparam [6:0] DR_SEQ [DR_NUM-1:0] = {ETH_DR_MODE_10GE-1, CPRI_DR_MODE_24G_RSFEC};
The below RTL snippet shows the Ethernet – CPRI Protocols testbench localparams to customize: 
localparam ETH_DR_MODE_25GE_1	 = 6'b00_00_00;
localparam ETH_DR_MODE_10GE_1     = 6'b00_00_01;
localparam CPRI_DR_MODE_24G_RSFEC = 6'b00_00_10;
localparam CPRI_DR_MODE_24G  	 = 6'b00_00_11;
localparam CPRI_DR_MODE_12G_RSFEC = 6'b00_01_00;
localparam CPRI_DR_MODE_12G   	= 6'b00_01_01;
localparam CPRI_DR_MODE_10G_RSFEC = 6'b00_01_10;
localparam CPRI_DR_MODE_10G       = 6'b00_01_11;
localparam CPRI_DR_MODE_9P8G      = 6'b00_10_00;
localparam CPRI_DR_MODE_6G        = 6'b00_10_01;
localparam CPRI_DR_MODE_4P9G      = 6'b00_10_10;
localparam CPRI_DR_MODE_3G        = 6'b00_10_11;
localparam CPRI_DR_MODE_2P4G      = 6'b00_11_00;
localparam CPRI_DR_MODE_1G        = 6'b00_11_01;

localparam DR_NUM = 3;
localparam [6:0] DR_SEQ [DR_NUM-1 : 0] = {CPRI_DR_MODE_4P9G,CPRI_DR_MODE_24G_RSFEC,ETH_DR_MODE_10GE_1};

The below RTL snippet shows the Ethernet – CPRI Protocols (with 1GE) testbench localparams to customize:

localparam ETH_DR_MODE_25GE_1      = 6'b00_00_00;
localparam ETH_DR_MODE_10GE_1      = 6'b00_00_01;
localparam CPRI_DR_MODE_24G_RSFEC  = 6'b00_00_10;
localparam CPRI_DR_MODE_24G        = 6'b00_00_11;
localparam CPRI_DR_MODE_12G_RSFEC  = 6'b00_01_00;
localparam CPRI_DR_MODE_12G        = 6'b00_01_01;
localparam CPRI_DR_MODE_10G_RSFEC  = 6'b00_01_10;
localparam CPRI_DR_MODE_10G        = 6'b00_01_11;
localparam CPRI_DR_MODE_9P8G       = 6'b00_10_00;
localparam CPRI_DR_MODE_6G         = 6'b00_10_01;
localparam CPRI_DR_MODE_4P9G       = 6'b00_10_10;
localparam CPRI_DR_MODE_3G         = 6'b00_10_11;
localparam CPRI_DR_MODE_2P4G       = 6'b00_11_00;
localparam CPRI_DR_MODE_1G         = 6'b00_11_01;
localparam ETH_DR_MODE_1GE_1       = 6'b00_11_10;

localparam DR_NUM = 3;
localparam [6:0] DR_SEQ [DR_NUM-1 : 0] = {ETH_DR_MODE_25GE_1,CPRI_DR_MODE_24G_RSFEC,ETH_DR_MODE_1GE_1};
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