AN 964: Signal Tap Tutorial for Intel Agilex® 7 Partial Reconfiguration Designs

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ID 710463
Date 10/02/2023
Public
Document Table of Contents
Document Table of Contents x
1. Tutorial Overview 2. Tutorial Walkthrough 3. Tutorial Results 4. AN 964: Signal Tap Tutorial for Intel Agilex® 7 Partial Reconfiguration Design Archives 5. AN 964: Signal Tap Tutorial for Intel Agilex® 7 Partial Reconfiguration Design Revision History
1. Tutorial Overview x
1.1. PR Debug Considerations 1.2. Tutorial Software and Hardware Requirements 1.3. Tutorial Design Description 1.4. Downloading the Tutorial Design
1.4. Downloading the Tutorial Design x
1.4.1. Tutorial Design Files
2. Tutorial Walkthrough x
Process Description Tutorial Steps 2.1. Step 1: Getting Started 2.2. Step 2: Preparing the Base Revision 2.3. Step 3: Preparing the Implementation Revisions for Debugging 2.4. Step 4: Configuring Signal Tap Logic Analyzer 2.5. Step 5: Generating Programming Files 2.6. Step 6: Programming the FPGA Device 2.7. Step 7: Performing Data Acquisition
2.2. Step 2: Preparing the Base Revision x
2.2.1. Preparing the Static Region 2.2.2. Preparing the Default PR Persona
2.4. Step 4: Configuring Signal Tap Logic Analyzer x
2.4.1. Tapping Signals in the Implementation Persona 2.4.2. Configuring Data Acquisition 2.4.3. Setting Trigger Conditions
2.4.2. Configuring Data Acquisition x
2.4.2.1. Add Acquisition Clock 2.4.2.2. Add Storage Parameters
3. Tutorial Results x
3.1. Waveforms for Slow Implementation 3.2. Waveforms for Default Implementation 3.3. Waveforms for Empty Implementation
1. Tutorial Overview
2. Tutorial Walkthrough
3. Tutorial Results
4. AN 964: Signal Tap Tutorial for Intel Agilex® 7 Partial Reconfiguration Design Archives
5. AN 964: Signal Tap Tutorial for Intel Agilex® 7 Partial Reconfiguration Design Revision History

2. Tutorial Walkthrough

This tutorial describes preparing the blinking_led design for debug with the Signal Tap Logic Analyzer.
This Application Note does not describe turning a non-PR design to a PR design. Refer to AN 953: Partially Reconfiguring a Design on an Intel Agilex® 7 FPGA Development Board for examples of the following tasks:
  • Creating a design partition
  • Allocating placement and routing regions for a PR partition
  • Defining personas
  • Creating project revisions
  • Preparing PR implementation revisions

Process Description

To tap signals in a PR design, you extend the debug fabric to the PR regions when creating the base revision, and then define debug components for the implementation revisions.

Tutorial Steps

This tutorial includes the following steps:


Section Content
Step 1: Getting Started
Step 2: Preparing the Base Revision
Step 3: Preparing the Implementation Revisions for Debugging
Step 4: Configuring Signal Tap Logic Analyzer
Step 5: Generating Programming Files
Step 6: Programming the FPGA Device
Step 7: Performing Data Acquisition

Related Information
Level Two Title