AN 964: Signal Tap Tutorial for Intel Agilex® 7 Partial Reconfiguration Designs

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ID 710463
Date 10/02/2023
Public
Document Table of Contents
Document Table of Contents x
1. Tutorial Overview 2. Tutorial Walkthrough 3. Tutorial Results 4. AN 964: Signal Tap Tutorial for Intel Agilex® 7 Partial Reconfiguration Design Archives 5. AN 964: Signal Tap Tutorial for Intel Agilex® 7 Partial Reconfiguration Design Revision History
1. Tutorial Overview x
1.1. PR Debug Considerations 1.2. Tutorial Software and Hardware Requirements 1.3. Tutorial Design Description 1.4. Downloading the Tutorial Design
1.4. Downloading the Tutorial Design x
1.4.1. Tutorial Design Files
2. Tutorial Walkthrough x
2.1. Step 1: Getting Started 2.2. Step 2: Preparing the Base Revision 2.3. Step 3: Preparing the Implementation Revisions for Debugging 2.4. Step 4: Configuring Signal Tap Logic Analyzer 2.5. Step 5: Generating Programming Files 2.6. Step 6: Programming the FPGA Device 2.7. Step 7: Performing Data Acquisition
2.2. Step 2: Preparing the Base Revision x
2.2.1. Preparing the Static Region 2.2.2. Preparing the Default PR Persona
2.4. Step 4: Configuring Signal Tap Logic Analyzer x
2.4.1. Tapping Signals in the Implementation Persona 2.4.2. Configuring Data Acquisition 2.4.3. Setting Trigger Conditions
2.4.2. Configuring Data Acquisition x
2.4.2.1. Add Acquisition Clock 2.4.2.2. Add Storage Parameters
3. Tutorial Results x
3.1. Waveforms for Slow Implementation 3.2. Waveforms for Default Implementation 3.3. Waveforms for Empty Implementation
1. Tutorial Overview
2. Tutorial Walkthrough
3. Tutorial Results
4. AN 964: Signal Tap Tutorial for Intel Agilex® 7 Partial Reconfiguration Design Archives
5. AN 964: Signal Tap Tutorial for Intel Agilex® 7 Partial Reconfiguration Design Revision History

2.6. Step 6: Programming the FPGA Device

Before you begin:
  1. Connect the power supply to the Intel Agilex® 7 F-Series or M-Series FPGA development board.
  2. Connect the USB Blaster cable between your PC USB port and the USB Blaster port on the development board.
Note: This tutorial utilizes the Intel Agilex® 7 F-Series or M-Series FPGA development board on the bench, outside of the PCIe* slot in your host machine.
To program the design on the board:
  1. In the Intel® Quartus® Prime software, click Tools > Programmer.
  2. In the Programmer, click Hardware Setup and select USB-Blaster
  3. Click Auto Detect and select the appropriate Intel Agilex® 7 device for your development board.
  4. Click OK. The Intel® Quartus® Prime software detects and updates the Programmer with the FPGA devices on the board.
  5. Select the appropriate Intel Agilex® 7 device for your development board and click Change File and load the blinking_led.sof file.
  6. Enable Program/Configure for blinking_led.sof file.
  7. Click Start and wait for the progress bar to reach 100%.
  8. To program the PR persona that you want to debug, right-click the blinking_led.sof file in the Programmer, and click Add PR Programming File.
  9. Select the blinking_led_slow.pr_partition.rbf file.
  10. Disable Program/Configure for the blinking_led.sof file.
  11. Enable Program/Configure for blinking_led_slow.pr_partition.rbf file and click Start.
  12. On the board, verify that two of the LEDs are blinking slower than the other two.
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