Visible to Intel only — GUID: skg1643117775632
Ixiasoft
2.1. Step 1: Getting Started
2.2. Step 2: Preparing the Base Revision
2.3. Step 3: Preparing the Implementation Revisions for Debugging
2.4. Step 4: Configuring Signal Tap Logic Analyzer
2.5. Step 5: Generating Programming Files
2.6. Step 6: Programming the FPGA Device
2.7. Step 7: Performing Data Acquisition
Visible to Intel only — GUID: skg1643117775632
Ixiasoft
2.4. Step 4: Configuring Signal Tap Logic Analyzer
In this step, you configure Signal Tap Logic Analyzer for each revision.
Revision | Signal Tap File Name |
---|---|
blinking_led_slow | stp_slow.stp |
blinking_led_default | stp_default.stp |
blinking_led_empty | stp_empty.stp |
Repeat the following steps for each revision:
- Set the current revision in the Intel® Quartus® Prime GUI.
- Open the Signal Tap file that corresponds to the set revision.
- Tap signals in the implementation persona.
- Configure data acquisition, including the acquisition clock and storage parameters.
- Set the trigger conditions for recording data.
- Save your changes before you continue to compiling the design.