AN 964: Signal Tap Tutorial for Intel Agilex® 7 Partial Reconfiguration Designs

ID 710463
Date 10/02/2023
Public
Document Table of Contents

1.3. Tutorial Design Description

The design for this tutorial consists of one 32-bit counter. At the board level, the design connects the clock to a 50MHz source, and connects the output to four LEDs on the FPGA. Selecting the output from the counter bits in a specific sequence causes the LEDs to blink at a specific frequency.
Figure 2. Flat Reference Design without PR Partitioning