F-Tile DisplayPort Intel® FPGA IP Design Example User Guide

ID 709308
Date 6/06/2024
Public
Document Table of Contents

2. DisplayPort Intel® FPGA IP Design Examples

The DisplayPort Intel FPGA IP design examples demonstrate parallel loopback from DisplayPort RX instance to DisplayPort TX instance without a Pixel Clock Recovery (PCR) module.

The DisplayPort Intel® FPGA IP TX-only design example demonstrates the DisplayPort source transmitting a fixed video resolution.

The DisplayPort Intel® FPGA IP RX-only design example demonstrates the DisplayPort sink receiving video frame from external sources.

Table 4.  DisplayPort Intel® FPGA IP Design Example for Agilex™ 7 F-Tile Devices
Design Example Designation Data Rate Channel Mode Loopback Type
DisplayPort SST parallel loopback without PCR DisplayPort SST RBR, HBR, HBR2, HBR3, UHBR10, UHBR13.5, UHBR20 Simplex Parallel without PCR
DisplayPort SST parallel loopback with AXIS Video Interface DisplayPort SST RBR, HBR, HBR2, HBR3, UHBR10, UHBR13.5, UHBR20 Simplex Parallel with AXIS Video Interface
DisplayPort SST TX-only DisplayPort SST RBR, HBR, HBR2, HBR3, UHBR10, UHBR13.5, UHBR20 Simplex
DisplayPort SST RX-only DisplayPort SST RBR, HBR, HBR2, HBR3, UHBR10, UHBR13.5, UHBR20 Simplex
Note: The Bitec Rev8 FMC is capable of UHBR20 RX, but is limited to UHB10 TX. As such, the DisplayPort Design Examples are limited to UHBR10 for TX operation. For more information, and to enable UHBR13.5 and UHBR20 TX, contact Intel Premier Support and quote 15015768814.
Note: In the IP Parameter Editor at the DisplayPort Source, you can see and instantiate 13.5 Gbps and 20 Gbps in the drop-down menu of the TX maximum link rate. For this release, the readiness of these data rates is for the early access with compilation only.