2.6. Interface Signals and Parameters
The tables below list the signals and parameter for the DisplayPort Intel® FPGA IP design example.
Parameter | Value | Description |
---|---|---|
RX_MAX_LANE_COUNT | 1, 2 or 4 | DP Rx Maximum Lane Count |
TX_MAX_LANE_COUNT | 1, 2 or 4 | DP Tx Maximum Lane Count |
RX_MAX_LINK_RATE | 1, 2, 4, 6, 10, 20, 30 (decimal) | DP Rx Maximum Data Rate 6: RBR, 10 :HBR, 20: HBR2, 30: HBR3, 1: UHBR10, 2: UHBR20 4: UHBR13.5 |
TX_MAX_LINK_RATE | 1, 2, 4, 6, 10, 20, 30 (decimal) | DP Tx Maximum Data Rate 6: RBR, 10: HBR, 20: HBR2, 30: HBR3, 1: UHBR10, 2: UHBR20 4: UHBR13.5 |
RX_PMA_WIDTH | 20, 40, 64 | DP Rx Parallel Data width RBR-HBR2: 20bits HBR3-UHBR10: 40bits UHBR13.5-UHBR20: 64 bits |
TX_PMA_WIDTH | 20, 40, 64 | DP TX Parallel Data width RBR-HBR2: 20bits HBR3-UHBR10: 40bits UHBR13.5-UHBR20: 64 bits |
RX_VIDEO_BPC | 6, 8, 10, 12, 16 | DP RX Video Bit per Component |
TX_VIDEO_BPC | 6, 8, 10, 12, 16 | DP TX Video Bit per Component |
Signal | Direction | Width | Description |
---|---|---|---|
On-board Oscillator Signal | |||
fgt_refclk_150 | Input | 1 | 150 MHz clock source used as System PLL reference clock |
core_refclk_100 | Input | 1 | 100 MHz clock source used as IOPLL reference clock and Avalon® memory-mapped management clock |
User Push Buttons and LEDs | |||
user_pb[0] | Input | 1 | Push button to trigger MSA print out during debug |
cpu_resetn | Input | 1 | Global reset |
DisplayPort FMC Daughter Card Pins (This Design Example is using FMC A) | |||
fmc_rx_p/n | Input | N | DisplayPort RX serial data
Note: N = RX maximum lane count
|
fmc_tx_p/n | Output | N | DisplayPort TX serial data
Note: N = TX maximum lane count
|
fmc_dp_rx_cable_detect | Input | 1 | DisplayPort RX cable detect |
1 = Cable detected | |||
0 = Cable not detected | |||
fmc_dp_rx_pwr_detect | Input | 1 | DisplayPort RX power detect |
1 = Power not detected | |||
0 = Power detected | |||
fmc_dp_rx_aux_in | Input | 1 | DisplayPort RX Aux In |
fmc_dp_rx_aux_out | Output | 1 | DisplayPort RX Aux Out |
fmc_dp_rx_aux_oe | Output | 1 | DisplayPort RX Aux OE |
fmc_dp_rx_hpd | Output | 1 | DisplayPort RX HPD |
1 = HPD asserted | |||
0 = HPD deasserted | |||
fmc_dp_tx_hpd | Input | 1 | DisplayPort TX HPD |
1 = HPD asserted | |||
0 = HPD deasserted | |||
fmc_dp_tx_aux_in | Input | 1 | DisplayPort TX Aux In |
fmc_dp_tx_aux_out | Output | 1 | DisplayPort TX Aux Out |
fmc_dp_tx_aux_oe | Output | 1 | DisplayPort TX Aux OE |
fmc_dp_tx_cad | Output | 1 | TX CAD for Bitec FMC |
Signal | Direction | Width | Description |
---|---|---|---|
Clock and Reset | |||
mgmt_clk_in_clk | Input | 1 | 100 MHz clock to CPU sub-system |
cpu_reset_bridge_in_reset_n | Input | 1 | Reset to CPU sub-system (active low) |
DisplayPort RX Signals | |||
dp_rx_reset_bridge_in_reset_n | Input | 1 | Reset to RX sub-system (active low) |
dp_rx_clk_16_in_clk | Input | 1 | RX Auxiliary clock (16 MHz) |
dp_rx_pio_0_in_port | Input | 1 | Push button I/O for debug purpose |
dp_rx_dp_sink_rx_audio_valid | Output | 1 | RX Audio Interface |
dp_rx_dp_sink_rx_audio_mute | Output | 1 |
Note: M = RX audio channel
|
dp_rx_dp_sink_rx_audio_infoframe | Output | 40 | — |
dp_rx_dp_sink_rx_audio_lpcm_data | Output | M*32 | — |
dp_rx_dp_sink_rx_aux_in | Input | 1 | RX auxiliary interface |
dp_rx_dp_sink_rx_aux_out | Output | 1 | |
dp_rx_dp_sink_rx_aux_oe | Output | 1 | |
dp_rx_dp_sink_rx_hpd | Output | 1 | RX HPD |
dp_rx_dp_sink_rx_cable_detect | Input | 1 | RX cable detect (active high) |
dp_rx_dp_sink_rx_pwr_detect | Input | 1 | RX power detect (active high) |
dp_rx_dp_sink_rx_msa | Output | 217 | DisplayPort RX MSA |
dp_rx_dp_sink_rx_lane_count | Output | 5 | DisplayPort RX lane count |
dp_rx_dp_sink_rx_link_rate_8bits | Output | 8 | RX Link Rate 8-bit indicator, used in transceiver reconfiguration management |
RBR: 0x06 | |||
HBR: 0x0A | |||
HBR2: 0x14 | |||
HBR3: 0x1E | |||
UHBR10: 0x01 | |||
UHBR13.5: 0x04 | |||
UHBR20: 0x02 | |||
dp_rx_dp_sink_rx_ss_valid | Output | 1 | DisplayPort RX secondary stream interface |
dp_rx_dp_sink_rx_ss_data | Output | 160 | |
dp_rx_dp_sink_rx_ss_sop | Output | 1 | |
dp_rx_dp_sink_rx_ss_eop | Output | 1 | |
dp_rx_dp_sink_rx_ss_clk | Output | 1 | |
dp_rx_dp_sink_rx_vid_clk | Input | 1 | DisplayPort RX video stream interface. |
dp_rx_dp_sink_rx_vid_sol | Output | 1 |
Note: B = RX bits per color, P = RX pixels per clock
|
dp_rx_dp_sink_rx_vid_eol | Output | 1 | — |
dp_rx_dp_sink_rx_vid_sof | Output | 1 | — |
dp_rx_dp_sink_rx_vid_eof | Output | 1 | — |
dp_rx_dp_sink_rx_vid_locked | Output | 1 | — |
dp_rx_dp_sink_rx_vid_interlace | Output | 1 | — |
dp_rx_dp_sink_rx_vid_field | Output | 1 | — |
dp_rx_dp_sink_rx_vid_overflow | Output | 1 | — |
dp_rx_dp_sink_rx_vid_data | Output | B*P*3 | — |
dp_rx_dp_sink_rx_vid_valid | Output | P | — |
dp_rx_dp_sink_rx_parallel_data | Input | N *S*10 | DisplayPort parallel data from RX Direct PHY
Note: N = RX maximum lane count, S = RX symbols per clock
|
dp_rx_dp_sink_rx_std_clkout | Input | N | CDR clock out from RX Direct PHY
Note: N = RX maximum lane count
|
dp_rx_dp_sink_rx_reconfig_req | Output | 1 | Transceiver reconfiguration interface to the RX reconfiguration management module |
dp_rx_dp_sink_rx_reconfig_ack | Input | 1 |
Note: N = RX maximum lane count
|
dp_rx_dp_sink_rx_reconfig_busy | Input | 1 | — |
dp_rx_dp_sink_rx_bitslip | Output | N | — |
dp_rx_dp_sink_rx_cal_busy | input | N | — |
dp_rx_dp_sink_rx_analogreset | Output | N | — |
dp_rx_dp_sink_rx_digitalreset | Output | N | — |
dp_rx_dp_sink_rx_is_lockedtoref | Input | N | — |
dp_rx_dp_sink_rx_is_lockedtodata | Input | N | — |
dp_rx_dp_sink_rx_set_locktoref | Output | N | — |
dp_rx_dp_sink_rx_set_locktodata | Output | N | — |
DisplayPort TX Signals | |||
dp_tx_reset_bridge_in_reset_n | Input | 1 | Reset to TX sub-system |
dp_tx_clk_16_in_clk | Input | 1 | TX Auxiliary clock (16 MHz) |
dp_tx_dp_source_clk_cal | Input | 1 | TX reconfiguration calibration clock |
dp_tx_dp_source_tx_audio_valid | Input | 1 | TX audio channel interface |
dp_tx_dp_source_tx_audio_mute | Input | 1 |
Note: M = TX audio channel
|
dp_tx_dp_source_tx_audio_lpcm_data | Input | M*32 | — |
dp_tx_dp_source_tx_audio_clk | Input | 1 | — |
dp_tx_dp_source_tx_aux_in | Input | 1 | TX auxiliary interface |
dp_tx_dp_source_tx_aux_out | Output | 1 | |
dp_tx_dp_source_tx_aux_oe | Output | 1 | |
dp_tx_dp_source_tx_hpd | Input | 1 | TX HPD |
dp_tx_dp_source_tx_link_rate_8bits | Output | 8 | TX Link Rate 8-bit indicator, used in transceiver reconfiguration management |
RBR: 0x06 | |||
HBR: 0x0A | |||
HBR2: 0x14 | |||
HBR3: 0x1E | |||
UHBR10: 0x01 | |||
UHBR13.5: 0x04 | |||
UHBR20: 0x02 | |||
dp_tx_dp_source_tx_ss_ready | Output | 1 | DisplayPort TX secondary stream interface |
dp_tx_dp_source_tx_ss_valid | Input | 1 | |
dp_tx_dp_source_tx_ss_data | Input | 128 | |
dp_tx_dp_source_tx_ss_sop | Input | 1 | |
dp_tx_dp_source_tx_ss_eop | Input | 1 | |
dp_tx_dp_source_tx_ss_clk | Output | 1 | |
dp_tx_dp_source_tx_vid_clk | Input | 1 | DisplayPort TX video stream (VYSNC/HSYNC/DE) interface (only used when TX_SUPPORT_IM_ENABLE = 0) |
dp_tx_dp_source_tx_vid_data | Input | B*P*3 |
Note: B = TX bits per color, P = TX pixels per clock
|
dp_tx_dp_source_tx_vid_v_sync | Input | P | — |
dp_tx_dp_source_tx_vid_h_sync | Input | P | — |
dp_tx_dp_source_tx_vid_de | Input | P | — |
dp_tx_dp_source_tx_im_clk | Input | 1 | DisplayPort TX video image interface (only used when TX_SUPPORT_IM_ENABLE = 1) |
dp_tx_dp_source_tx_im_sol | Input | 1 |
Note: B = TX bits per color, P = TX pixels per clock
|
dp_tx_dp_source_tx_im_eol | Input | 1 | — |
dp_tx_dp_source_tx_im_sof | Input | 1 | — |
dp_tx_dp_source_tx_im_eof | Input | 1 | — |
dp_tx_dp_source_tx_im_data | Input | B*P*3 | — |
dp_tx_dp_source_tx_im_valid | Input | 1 | — |
dp_tx_dp_source_tx_im_locked | Input | 1 | — |
dp_tx_dp_source_tx_im_interlace | Input | 1 | — |
dp_tx_dp_source_tx_im_field | Input | 1 | — |
dp_tx_dp_source_tx_parallel_data | Output | N*S*10 | DisplayPort parallel data to TX Direct PHY |
Note: N = TX maximum lane count, S = TX symbols per clock
|
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dp_tx_dp_source_tx_std_clkout | Input | N | TX Direct PHY clock out |
Note: N = TX maximum lane count
|
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dp_tx_dp_source_tx_pll_locked | Input | 1 | TX PLL locked indicator |
dp_tx_dp_source_tx_reconfig_req | Output | 1 | Transceiver Reconfiguration interface to TX reconfiguration management module |
dp_tx_dp_source_tx_reconfig_ack | Input | 1 |
Note: N = TX maximum lane count
|
dp_tx_dp_source_tx_reconfig_busy | Input | 1 | — |
dp_tx_dp_source_tx_pll_powerdown | Output | 1 | — |
dp_tx_dp_source_tx_analog_reconfig_req | Output | 1 | — |
dp_tx_dp_source_tx_analog_reconfig_ack | Input | 1 | — |
dp_tx_dp_source_tx_analog_reconfig_busy | Input | 1 | — |
dp_tx_dp_source_tx_vod | Output | N*2 | — |
dp_tx_dp_source_tx_emp | Output | N*2 | — |
dp_tx_dp_source_tx_analogreset | Output | N | — |
dp_tx_dp_source_tx_digitalreset | Output | N | — |
dp_tx_dp_source_tx_cal_busy | Input | N | — |
Signal | Direction | Width | Description |
---|---|---|---|
mgmt_clk | Input | 1 | RX reconfiguration management clock (100 MHz) |
system_pll_clk | Input | 1 | DirectPhy System PLL reference clock from System PLL module |
gxb_refclk | Input | 1 | RX Direct PHY CDR reference clock. This design example uses 135 MHz |
sys_resetn | Input | 1 | RX Direct PHY reset (active low) |
dp_rx_link_rate | Input | 8 | RX link rate indicator, used in transceiver reconfiguration management |
dp_rx_reconfig_en | Output | 1 | RX reconfiguration enable signal |
dp_rx_rate_recfg_req | Input | 1 | Transceiver Reconfiguration interface from the DisplayPort RX core |
dp_rx_rate_recfg_ack | Output | N |
Note: N = RX maximum lane count (1, 2, or 4)
|
dp_rx_rate_recfg_busy | Output | 1 | — |
gxb_rx_clkout | Output | N | RX Direct PHY CDR clock out
Note: N = RX maximum lane count (1, 2, or 4)
|
gxb_rx_serial_data/gxb_rx_serial_data_n | Input | N | DisplayPort Serial Data to RX Direct PHY
Note: N = RX maximum lane count (1, 2, or 4)
|
dp_rx_parallel_data | Output | S | DisplayPort parallel data to DisplayPort RX core
Note: S=PMA_WIDTH (20, 40. 64)
|
dp_rx_is_lockedtoref | Output | N | — |
dp_rx_is_lockedtodata | Output | N | — |
dp_rx_cal_busy | Output | 1 | — |
Signal | Direction | Width | Description |
---|---|---|---|
mgmt_clk | Input | 1 | RX reconfiguration management clock (100 MHz) |
system_pll_clk | Input | 1 | DirectPhy System PLL reference clock from System PLL module |
gxb_refclk | Input | 1 | RX Direct PHY CDR reference clock. This design example uses 135 MHz |
sys_resetn | Input | 1 | RX Direct PHY reset (active low) |
tx_cad | Output | 1 | Driven to FMC card TX CAD. Tied to 0 |
dp_tx_link_rate | Input | 8 | TX Link Rate indicator, used in transceiver reconfiguration management |
dp_tx_reconfig_en | Output | 1 | TX reconfiguration enable signal |
dp_tx_cal_busy | Input | N | — |
gxb_tx_clkout | Output | N | Transceiver clock out
Note: N = TX maximum lane count (1, 2, or 4)
|
gxb_tx_serial_data / gxb_tx_serial_data_n | Output | N | DisplayPort Serial Data from Transceiver
Note: N = TX maximum lane count
|
dp_tx_parallel_data | Input | S | DisplayPort Parallel Data from DisplayPort TX Core
Note: S=PMA_WIDTH (20, 40, 64)
|
dp_tx_anlg_recfg_req | Input | 1 | Transceiver Reconfiguration interface from DisplayPort TX Core |
dp_tx_anlg_recfg_ack | Output | 1 |
Note: N = TX maximum lane count (1, 2, or 4)
|
dp_tx_anlg_rcfg_vod | Input | 8 | — |
dp_tx_anlg_rcfg_emp | Input | 8 | — |
dp_tx_rate_recfg_req | Input | 1 | — |
dp_tx_rate_recfg_ack | Output | 1 | — |
dp_tx_rate_recfg_busy | Output | 1 | — |
dp_tx_cal_busy | Output | N | — |