F-Tile DisplayPort Intel® FPGA IP Design Example User Guide

ID 709308
Date 6/06/2024
Public
Document Table of Contents

2.4. Design Components

The DisplayPort Intel® FPGA IP design example requires the following components.
Table 5.  Core System Components
Module Description
Core System (Platform Designer)

The core system consists of the Nios® V Processor and its necessary components, DisplayPort RX and TX core sub-systems.

This system provides the infrastructure to interconnect the Nios® V processor with the DisplayPort Intel FPGA IP (RX and TX instances) through Avalon® memory-mapped interface within a single Platform Designer system to ease the software build flow.

This system consists of:

  • CPU Sub-System
  • RX Sub-System
  • TX Sub-System
RX Sub-System (Platform Designer)

The RX sub-system consists of:

  • Clock Source—The clock source to the DisplayPort RX core. This sub-system has two clock sources integrated: 100 MHz and 16 MHz.
  • Reset Bridge—The bridge that connects the external signal to the sub-system. This bridge synchronizes to the respective clock source before it is used.
  • DisplayPort RX Core—DisplayPort Sink IP core, VESA DisplayPort Standard version 2.0.
  • Debug FIFO—This FIFO captures all DisplayPort RX auxiliary cycles, and prints out in the Nios® V Debug terminal.
  • PIO—The parallel I/O that triggers the MSA capture, and prints out when the on-board push button (PB) is pressed.
  • Avalon® memory-mapped Pipeline Bridge—This Avalon® memory-mapped bridge interconnects the Avalon® memory-mapped interface between components within the RX sub-system to the Nios® V processor in the Core sub-system.
  • EDID—The EDID RAM is only used to store the desired EDID value in the RAM and connect to the DisplayPort Sink IP core. This component is only used when you disable the Enable GPU Control option in the RX core.
TX Sub-System (Platform Designer)

The TX sub-system consists of:

  • Clock Source—The clock source to the DisplayPort TX core. This sub-system has two clock sources integrated: 100 MHz and 16 MHz.
  • Reset Bridge—The bridge that connects the external signal to the sub-system. This bridge synchronizes to the respective clock source before it is used.
  • DisplayPort TX Core—DisplayPort Source IP core, VESA DisplayPort Standard version 2.0.
  • Debug FIFO—This FIFO captures all DisplayPort TX auxiliary cycles, and prints out in the Nios® V Debug terminal. This component is only used when the TX_AUX_DEBUG parameter is turned on.
  • PIO—The parallel I/O that triggers the DPTX register update in software (tx_utils.c).
  • Avalon® memory-mapped Pipeline Bridge—This Avalon® memory-mapped bridge interconnects the Avalon® memory-mapped interface between components within the TX sub-system to the Nios® V processor in the Core sub-system.
Table 6.  DisplayPort RX PHY Top and TX PHY Top Components
Module Description
RX PHY Top

The RX PHY top level consists of the components related to the receiver PHY layer.

  • DisplayPort DirectPHY Building Block (RX)—The transceiver block that receives the serial data from an external video source and deserializes it to 20-bit (HBR2 and below), 40-bit (HBR3 and UHBR10), or 64-bit (UHBR13.5 and UHBR20) parallel data to the DisplayPort sink IP core. This block supports up to 20 Gbps (UHBR20) data rate with 4 channels. DP Reconfiguration management are implemented within this Building Block.
  • FIFO – To manage Parallel Data transfer crossing between LS_CLK domain and SYS_PLL clock domain.
TX PHY Top

The TX PHY top level consists of the components related to the transmitter PHY layer.

  • Transceiver Direct PHY (TX)—The transceiver block that receives 20-bit, 40-bit, or 64-bit parallel data from the DisplayPort Intel® FPGA IP and serializes the data before transmitting it. This block supports up to 20 Gbps (UHBR20) data rate with 4 channels. DP Reconfiguration management are implemented within this Building Block.
  • FIFO – To manage Parallel Data transfer crossing between LS_CLK domain and SYS_PLL clock domain.
Table 7.  Top-Level Common Blocks
Module Description
System PLL DisplayPort Design Example is using System PLL as Transceiver reference clock source.
  • The minimum System PLL output frequency to support all DisplayPort rate is 320 MHz. This design example uses a 900 MHz (highest) output frequency so that SysPLL refclk can be shared with rx/tx refclk_link which is 150 MHz.