Core System (Platform Designer) |
The core system consists of the Nios® V Processor and its necessary components, DisplayPort RX and TX core sub-systems. This system provides the infrastructure to interconnect the Nios® V processor with the DisplayPort Intel FPGA IP (RX and TX instances) through Avalon® memory-mapped interface within a single Platform Designer system to ease the software build flow. This system consists of:
- CPU Sub-System
- RX Sub-System
- TX Sub-System
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RX Sub-System (Platform Designer) |
The RX sub-system consists of:
- Clock Source—The clock source to the DisplayPort RX core. This sub-system has two clock sources integrated: 100 MHz and 16 MHz.
- Reset Bridge—The bridge that connects the external signal to the sub-system. This bridge synchronizes to the respective clock source before it is used.
- DisplayPort RX Core—DisplayPort Sink IP core, VESA DisplayPort Standard version 2.0.
- Debug FIFO—This FIFO captures all DisplayPort RX auxiliary cycles, and prints out in the Nios® V Debug terminal.
- PIO—The parallel I/O that triggers the MSA capture, and prints out when the on-board push button (PB) is pressed.
- Avalon® memory-mapped Pipeline Bridge—This Avalon® memory-mapped bridge interconnects the Avalon® memory-mapped interface between components within the RX sub-system to the Nios® V processor in the Core sub-system.
- EDID—The EDID RAM is only used to store the desired EDID value in the RAM and connect to the DisplayPort Sink IP core. This component is only used when you disable the Enable GPU Control option in the RX core.
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TX Sub-System (Platform Designer) |
The TX sub-system consists of:
- Clock Source—The clock source to the DisplayPort TX core. This sub-system has two clock sources integrated: 100 MHz and 16 MHz.
- Reset Bridge—The bridge that connects the external signal to the sub-system. This bridge synchronizes to the respective clock source before it is used.
- DisplayPort TX Core—DisplayPort Source IP core, VESA DisplayPort Standard version 2.0.
- Debug FIFO—This FIFO captures all DisplayPort TX auxiliary cycles, and prints out in the Nios® V Debug terminal. This component is only used when the TX_AUX_DEBUG parameter is turned on.
- PIO—The parallel I/O that triggers the DPTX register update in software (tx_utils.c).
- Avalon® memory-mapped Pipeline Bridge—This Avalon® memory-mapped bridge interconnects the Avalon® memory-mapped interface between components within the TX sub-system to the Nios® V processor in the Core sub-system.
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