F-Tile DisplayPort Intel® FPGA IP Design Example User Guide

ID 709308
Date 6/06/2024
Public
Document Table of Contents

2.2. Agilex™ 7 F-Tile DisplayPort SST TX-only Design Features

The TX-only design example demonstrates the transmission of a single video stream from the Intel DisplayPort Source IP to an external DisplayPort Sink.
Figure 7.  Agilex™ 7 DisplayPort SST TX-only
  • To generate this TX-only variant, turn on the DisplayPort source TX SUPPORT DP parameter and turn off the DisplayPort sink RX SUPPORT DP parameter.
  • This variant uses the standard VSYNC/HSYNC/DE video interface, while the DisplayPort source’s TX SUPPORT IM ENABLE parameter is turned off.
  • For video source, this variant integrates Test Pattern Generator II and Clocked Video Output II to display 1080p60 color bar image.
  • The IOPLL drives the video clock at a 300 MHz to CVO II and 37.125 MHz (4 pixel per clock) to TPG II.
  • Before programming SOF file to the development kit, set OUT6 frequency of Si5391A to 150 MHz in the Clock Control GUI.