F-Tile DisplayPort Intel® FPGA IP Design Example User Guide

ID 709308
Date 6/06/2024
Public
Document Table of Contents

2.3. Agilex™ 7 F-Tile DisplayPort SST RX-only Design Features

This RX-only design example demonstrates the receiving of a single video stream by the Intel DisplayPort Sink IP, from an external DisplayPort Source.
Figure 8.  Agilex™ 7 DisplayPort SST RX-only
  • To generate this RX-only variant, turn on the DisplayPort sink RX SUPPORT DP and turn off the DisplayPort source TX SUPPORT DP parameters.
  • The IOPLL drives video clock at a fixed frequency (in this case, 300 MHz by default).
  • If you configure the DisplayPort sink MAX LINK RATE parameter to HBR3 or MAX LINK RATE parameter to HBR2 and PIXELS PER CLOCK to DUAL, the video clock runs at 300 MHz to support 4Kp60 pixel rate (594/2 = 297 MHz). Otherwise, the video clock runs at 160 MHz.
  • The DisplayPort sink receives video from an external video source such as a GPU and decodes it for the parallel video interface.