F-Tile DisplayPort Intel® FPGA IP Design Example User Guide

ID 709308
Date 6/06/2024
Public
Document Table of Contents

2.5. Clocking Scheme

The clocking scheme illustrates the clock domains in the DisplayPort Intel® FPGA IP design example.

Figure 9.  Agilex™ 7 F-Tile DisplayPort Transceiver Clocking Scheme
Table 8.  Clocking Scheme Signals
Clock in diagram Description
SysPLL refclk

F-Tile System PLL reference clock which can be any clock frequency that is dividable by System PLL for that output frequency.

In this design example, system_pll_clk_link and rx/tx refclk_link share the same 150 MHz SysPLL refclk.

It must be a free running clock which is connected from a dedicated transceiver reference clock pin to the input clock port of Reference and System PLL Clocks IP, before connecting the corresponding output port to DisplayPort Phy Top.
Note: For this design example, configure Clock Controller GUI Si5391A OUT6 to 150 MHz.
system_pll_clk_link

The minimum System PLL output frequency to support all DisplayPort rates is 320 MHz.

This design example uses a 900 MHz (highest) output frequency so that SysPLL refclk can be shared with rx/tx refclk_link, which is 150 MHz.

rx_cdr_refclk_link /

tx_pll_refclk_link
Rx CDR and Tx PLL Link refclk which is fixed to 150 MHz to support all DisplayPort data rates.

rx_ls_clkout /

tx_ls_clkout

DisplayPort Link Speed Clock to clock DisplayPort IP core. The frequency is equivalent to Data Rate divided by parallel data width.

Example:

Frequency = data rate / data width

For HBR3:

= 8.1G (HBR3) / 40 bits

= 202.5 MHz

For UHBR10:

= 10G (UHBR10) / 32 bits

= 312.5 MHz