F-Tile DisplayPort Intel® FPGA IP Design Example User Guide

Download PDF
ID 709308
Date 6/06/2024
Public
Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. DisplayPort Intel® FPGA IP Design Examples 3. HDCP Over DisplayPort Design Example 4. Document Revision History for F-Tile DisplayPort Intel® FPGA IP Design Example User Guide
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Regenerating ELF File
2. DisplayPort Intel® FPGA IP Design Examples x
2.1. Agilex™ 7 F-Tile DisplayPort SST Parallel Loopback Design Features 2.2. Agilex™ 7 F-Tile DisplayPort SST TX-only Design Features 2.3. Agilex™ 7 F-Tile DisplayPort SST RX-only Design Features 2.4. Design Components 2.5. Clocking Scheme 2.6. Interface Signals and Parameters
3. HDCP Over DisplayPort Design Example x
3.1. High-bandwidth Digital Content Protection (HDCP) 3.2. HDCP Over DisplayPort Design Example Architecture 3.3. Nios® V Processor Software Flow 3.4. Design Walkthrough 3.5. Protection of Encryption Key Embedded in FPGA Design 3.6. Debug Guidelines
3.4. Design Walkthrough x
3.4.1. Setting Up the Hardware 3.4.2. Generating the Design 3.4.3. Including HDCP Production Keys 3.4.4. Compiling the Design 3.4.5. Viewing the Results
3.4.3. Including HDCP Production Keys x
3.4.3.1. Storing Plain HDCP Production Keys in the FPGA (Support HDCP Key Management = 0) 3.4.3.2. Storing Encrypted HDCP Production Keys in the External Flash Memory or EEPROM (Support HDCP Key Management = 1)
3.4.3.1. Storing Plain HDCP Production Keys in the FPGA (Support HDCP Key Management = 0) x
3.4.3.1.1. HDCP Key Mapping from DCP Key Files 3.4.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files 3.4.3.1.3. hdcp2x_rx_kmem.v file 3.4.3.1.4. hdcp2x_tx_kmem.v file
3.4.3.2. Storing Encrypted HDCP Production Keys in the External Flash Memory or EEPROM (Support HDCP Key Management = 1) x
3.4.3.2.1. Intel KEYENC 3.4.3.2.2. Key Programmer
3.5. Protection of Encryption Key Embedded in FPGA Design x
3.5.1. Security Considerations
3.6. Debug Guidelines x
3.6.1. HDCP Status Signals 3.6.2. Modifying HDCP Software Parameters 3.6.3. Frequently Asked Questions (FAQ)
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. DisplayPort Intel® FPGA IP Design Examples
3. HDCP Over DisplayPort Design Example
4. Document Revision History for F-Tile DisplayPort Intel® FPGA IP Design Example User Guide

4. Document Revision History for F-Tile DisplayPort Intel® FPGA IP Design Example User Guide

Document Version Quartus® Prime Version IP Version Changes
2024.06.06 24.1 20.0.1
  • Corrected Native PHY to Direct PHY.
  • Added values to Top-Level Parameters
2024.04.09 24.1 20.0.1
  • Updated mentions of Nios® II to Nios® V (where applicable).
  • Added a note about obtaining Nios® V evaluation license in the Generating the Design topic.
2023.11.03 23.3 20.0.1
  • Added DisplayPort RX-only and DisplayPort TX-only to the list of available design examples.
  • Added the following chapters:
    • Agilex™ 7 F-Tile DisplayPort SST TX-only Design Features
    • Agilex™ 7 F-Tile DisplayPort SST RX-only Design Features
  • Added Agilex™ 7 I-Series SoC Development Kit FA and Agilex™ 7 I-Series SoC Development Kit FB to the list of boards.
  • Updated the link for customers to access HDCP feature.
2023.04.18 23.1 20.0.1
  • Updated the product family name to "Intel Agilex 7."
  • Added the following new topics:
    • HDCP Over DisplayPort Design Example for Agilex™ 7 Devices
    • Translating DisplayPort Link Training AUX Transactions
2022.10.21 22.3 20.0.1 Enabled DisplayPort 2.0 UHBR10 data rate in design examples.
2022.09.02 22.2 20.0.1
  • Changed document title from DisplayPort Intel Agilex F-Tile FPGA IP Design Example User Guide to F-Tile DisplayPort Intel FPGA IP Design Example User Guide.
  • Enabled AXIS Video Design Example variant.
  • Removed Static Rate design and replaced it with Multi Rate Design Example.
  • Removed the note in the DisplayPort Intel FPGA IP Design Example Quick Start Guide that says Intel Quartus Prime 21.4 software version only supports Preliminary Design Examples.
  • Replaced the Directory Structure figure with the correct figure.
  • Added a section Regenerating ELF File under Compiling and Testing the Design.
  • Updated the Hardware and Software Requirements section to include additional hardware requirements.
2021.12.13 21.4 20.0.0 Initial release.
Level Two Title