Visible to Intel only — GUID: cvb1474981518726
Ixiasoft
2.1. Stratix® 10 DisplayPort SST Parallel Loopback Design Features
2.2. Stratix® 10 DisplayPort SST TX-only or RX-only Design Features
2.3. Design Components
2.4. Clocking Scheme
2.5. Interface Signals and Parameters
2.6. Hardware Setup
2.7. Simulation Testbench
2.8. DisplayPort Transceiver Reconfiguration Flow
2.9. Transceiver Lane Configurations
Visible to Intel only — GUID: cvb1474981518726
Ixiasoft
2. Parallel Loopback Design Examples
The DisplayPort Intel® FPGA IP Parallel Loopback design examples demonstrates parallel loopback from DisplayPort RX instance to DisplayPort TX instance with or without a Pixel Clock Recovery (PCR) module.
Design Example | Designation | Data Rate | Channel Mode | Loopback Type |
---|---|---|---|---|
DisplayPort SST TX-only | DisplayPort SST | HBR3, HBR2, HBR, RBR, UHBR10, UHBR13.5, and UHBR20 | Simplex | - |
DisplayPort SST RX-only | DisplayPort SST | HBR3, HBR2, HBR, RBR, UHBR10, UHBR13.5, and UHBR20 | Simplex | - |
DisplayPort SST parallel loopback with PCR | DisplayPort SST | HBR3, HBR2, HBR, RBR, UHBR10, UHBR13.5, and UHBR20 | Simplex | Parallel with PCR |
DisplayPort SST parallel loopback without PCR | DisplayPort SST | HBR3, HBR2, HBR, RBR, UHBR10, UHBR13.5, and UHBR20 | Simplex | Parallel without PCR |
Note: The Bitec DisplayPort Revision 8 FMC daughter card does not support TX rates above UHBR10.
Section Content
Stratix 10 DisplayPort SST Parallel Loopback Design Features
Stratix 10 DisplayPort SST TX-only or RX-only Design Features
Design Components
Clocking Scheme
Interface Signals and Parameters
Hardware Setup
Simulation Testbench
DisplayPort Transceiver Reconfiguration Flow
Transceiver Lane Configurations