DisplayPort Stratix® 10 FPGA IP Design Example User Guide

ID 683887
Date 4/10/2024
Public
Document Table of Contents

2. Parallel Loopback Design Examples

The DisplayPort Intel® FPGA IP Parallel Loopback design examples demonstrates parallel loopback from DisplayPort RX instance to DisplayPort TX instance with or without a Pixel Clock Recovery (PCR) module.
Table 6.   DisplayPort Intel® FPGA IP Design Example for Stratix® 10 Devices
Design Example Designation Data Rate Channel Mode Loopback Type
DisplayPort SST TX-only DisplayPort SST HBR3, HBR2, HBR, RBR, UHBR10, UHBR13.5, and UHBR20 Simplex -
DisplayPort SST RX-only DisplayPort SST HBR3, HBR2, HBR, RBR, UHBR10, UHBR13.5, and UHBR20 Simplex -
DisplayPort SST parallel loopback with PCR DisplayPort SST HBR3, HBR2, HBR, RBR, UHBR10, UHBR13.5, and UHBR20 Simplex Parallel with PCR
DisplayPort SST parallel loopback without PCR DisplayPort SST HBR3, HBR2, HBR, RBR, UHBR10, UHBR13.5, and UHBR20 Simplex Parallel without PCR
Note: The Bitec DisplayPort Revision 8 FMC daughter card does not support TX rates above UHBR10.