Visible to Intel only — GUID: iie1474978763802
Ixiasoft
2.1. Stratix® 10 DisplayPort SST Parallel Loopback Design Features
2.2. Stratix® 10 DisplayPort SST TX-only or RX-only Design Features
2.3. Design Components
2.4. Clocking Scheme
2.5. Interface Signals and Parameters
2.6. Hardware Setup
2.7. Simulation Testbench
2.8. DisplayPort Transceiver Reconfiguration Flow
2.9. Transceiver Lane Configurations
Visible to Intel only — GUID: iie1474978763802
Ixiasoft
1.2. Hardware and Software Requirements
Intel uses the following hardware and software to test the design example.
Hardware
- Stratix® 10 GX FPGA L-tile or H-tile Development Kit
- DisplayPort Source (Graphics Processing Unit (GPU))
- DisplayPort Sink (Monitor)
- Bitec DisplayPort FMC daughter card (Revisions 8.0, 11.0, and 12.0)
- DisplayPort cables
Software
- Quartus® Prime Pro Edition (for hardware testing)
- Ashling RiscFree* integrated development environment (IDE) for Intel FPGAs
- Questa* Intel® FPGA Edition, Questa* Intel® FPGA Starter Edition, (Verilog only), Riviera-PRO* , Xcelium* or VCS* (Verilog only)/ VCS* MX simulator