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2.1. Stratix® 10 DisplayPort SST Parallel Loopback Design Features
2.2. Stratix® 10 DisplayPort SST TX-only or RX-only Design Features
2.3. Design Components
2.4. Clocking Scheme
2.5. Interface Signals and Parameters
2.6. Hardware Setup
2.7. Simulation Testbench
2.8. DisplayPort Transceiver Reconfiguration Flow
2.9. Transceiver Lane Configurations
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3.4.3.1.3. hdcp2x_rx_kmem.v file
For hdcp2x_rx_kmem.v file
- To identify the correct HDCP2 RX DCP key file for hdcp2x_rx_kmem.v, make sure the first 4 bytes of the file are “0x00, 0x00, 0x00, 0x02”.
- The keys in the DCP key files are in little-endian format.
Figure 20. Byte Mapping from HDCP2 RX DCP Key File into hdcp2x_rx_kmem.v
The following figure shows the exact byte mapping from HDCP2 RX DCP key file into hdcp2x_rx_kmem.v
Note: The byte number displays in the following format:
- Key size in bytes * key number + byte number in current row + constant offset + row size in bytes * row number.
- 862*n indicates that each key set has 862 bytes.
- 16*y indicates that each row has 16 bytes. There is an exception in cert_rx_prod where ROW 32 has only 10 bytes.
Figure 21. HDCP2 RX DCP Key File Filling with Junk Values
Figure 22. Wire Arrays of hdcp2x_rx_kmem.v
The following figure shows the wire arrays for hdcp2x_rx_kmem.v (cert_rx_prod, kprivrx_qinv_prod, and lc128_prod) map to the example of HDCP2 RX DCP key file in Figure 21.