Visible to Intel only — GUID: mca1574304644983
Ixiasoft
2.1. Stratix® 10 DisplayPort SST Parallel Loopback Design Features
2.2. Stratix® 10 DisplayPort SST TX-only or RX-only Design Features
2.3. Design Components
2.4. Clocking Scheme
2.5. Interface Signals and Parameters
2.6. Hardware Setup
2.7. Simulation Testbench
2.8. DisplayPort Transceiver Reconfiguration Flow
2.9. Transceiver Lane Configurations
Visible to Intel only — GUID: mca1574304644983
Ixiasoft
3. HDCP Over DisplayPort Design Example
The HDCP over DisplayPort hardware design example helps you to evaluate the functionality of the HDCP feature and enables you to use the feature in your Stratix® 10 designs.
Note: The HDCP feature is not included in the Quartus® Prime Pro Edition software. To access the HDCP feature, contact Intel at https://plan.seek.intel.com/psg_asmo_psgem_lpcs_en_2021_hdcp.
Note: The HDCP feature is not supported in DisplayPort 2.0 in this release.