F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Release Notes

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Date 7/08/2024
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1. F-Tile Avalon Streaming Intel FPGA IP for PCI Express* Release Notes
1. F-Tile Avalon Streaming Intel FPGA IP for PCI Express* Release Notes x
1.1. F-Tile Avalon Streaming Intel FPGA IP for PCI Express: IP Core v13.0.0 1.2. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v12.0.0 1.3. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v11.0.0 1.4. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v10.0.0 1.5. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v9.0.0 1.6. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v8.1.0 1.7. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v8.0.0 1.8. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v7.0.0 1.9. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v6.0.0 1.10. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v5.0.0 1.11. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v4.0.0 1.12. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v3.0.0 1.13. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v2.0.0 1.14. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : User Guide Archives
1. F-Tile Avalon Streaming Intel FPGA IP for PCI Express* Release Notes

1.11. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v4.0.0

Table 11.  F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP v4.0.0 : 2022.01.14
Quartus® Prime Version Description Impact
21.4

Warning messages clean-up for the F-Tile Avalon-ST PCIe Hard IP.

Allows you to focus on warning messages that require your attention.

Corrected signal type for pin_perst_n, p0_pin_perst_n in Platform Designer.

The signal regrouped into a more intuitive group based on the functionality that it provides. The Hard IP Status Interface is now enabled by default. No functional impact to existing customer is expected due to these changes.

Added Single Root I//O Virtualization design example variant and clean up timing warning for design examples.

This Single Root I//O Virtualization design example supports Gen3 x16 and Gen4 x16 Endpoint configurations.

Added support for Debug Toolkit while in Endpoint mode and using Linux OS and Windows.

Using the Debug Toolkit, you can:
  • Report protocol parameters on a per-port basis.
  • Read PHY status information.

Added Xcelium simulator support for the F-Tile Avalon-ST PCIe Hard IP in this release.

The design example generated for F-Tile Avalon Streaming PCIe Hard IP can be simulated using Xcelium simulator.

IP bugs fixed

You must regenerate any design using a F-Tile Avalon Streaming IP or Multi Channel DMA IP when moving from an earlier Quartus® Prime version to the 21.4 version.

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