F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Release Notes

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Date 7/08/2024
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1. F-Tile Avalon Streaming Intel FPGA IP for PCI Express* Release Notes
1. F-Tile Avalon Streaming Intel FPGA IP for PCI Express* Release Notes x
1.1. F-Tile Avalon Streaming Intel FPGA IP for PCI Express: IP Core v13.0.0 1.2. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v12.0.0 1.3. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v11.0.0 1.4. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v10.0.0 1.5. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v9.0.0 1.6. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v8.1.0 1.7. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v8.0.0 1.8. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v7.0.0 1.9. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v6.0.0 1.10. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v5.0.0 1.11. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v4.0.0 1.12. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v3.0.0 1.13. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v2.0.0 1.14. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : User Guide Archives
1. F-Tile Avalon Streaming Intel FPGA IP for PCI Express* Release Notes

1.12. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v3.0.0

Table 12.  F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP v3.0.0 : 2021.11.09
Quartus® Prime Version Description Impact
21.3

Warning messages cleaned up for the Avalon Streaming PIO design example.

Allow the user to focus on warning messages that require their attention.

Added PCIe Gen3/Gen4 x8 Avalon Streaming PIO Design Example Variant.

This design example supports Gen3 x8 and Gen4 x8 Endpoint configurations.

Fixed simulation issues associated with the Avalon Streaming PIO design example.

Regenerate the design example in Quartus® Prime v21.3 if the design example simulation does not run correctly.

The IP Parameter Editor GUI has been cleaned up and IP User Guide has been updated to reflect the change.

No functional impact is expected on existing users.

p*_flr_rcvd_pf_num_o and p*_flr_completed_pf_num_i signals are not required when Function Level Reset is enabled and Enable SR-IOV support is disabled. Hence, the signals are not exposed in Quartus® Prime v21.3 release.

No functional impact is expected on existing users.

Added 10-bit Tag Support Interface to indicate whether the 10-bit tag requester enable field is enabled in the configuration space (bit [12] of the Device Control 2 register)

No functional impact is expected on existing users, other than a new option provided for user to check the 10-bit tag requester enable field.

Added HCSL I/O standard support for PCIe IP refclk.

HCSL I/O standard is recommended for PCIe IP refclk. The design can now be compiled successfully with HCSL I/O standard for PCIe IP refclk.

The preset or default value for Gen 3 Requested equalization far-end TX preset vector and Gen 4 Requested equalization far-end TX preset vector has been updated in the IP Parameter Editor GUI.

The new preset or default values are recommended for most designs. Users should update the preset value to the new one if the F-Tile PCIe IP was generated in the previous Quartus® Prime software version that uses the old default value.

Added a message to remind user that p0_app_req_retry_en_i signal must be tied to zero when CvP is enabled for core_x16 (port0).

No functional impact is expected on existing users. The Config Retry Status (CRS) is handled by the IP depending on the CvP mode, p0_app_req_retry_en_i is not required when CvP is enabled.

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